High-Speed shortest path co-processor design
Shortest path algorithms are significant in graph theory and have been applied in many applications such as transportation and networking. Most of the shortest path calculation is performed on general purpose processor where instructions must be run to read the input, compute the result, and set the...
| Main Authors: | , , , , |
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| Format: | Conference or Workshop Item |
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2009
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| _version_ | 1825718656923860992 |
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| author | Idris, Mohd Yamani Idna Abu Bakar, Suraya Tamil, Emran Mohd Razak, Zaidi Noor, Noorzaily Mohamed |
| author_facet | Idris, Mohd Yamani Idna Abu Bakar, Suraya Tamil, Emran Mohd Razak, Zaidi Noor, Noorzaily Mohamed |
| author_sort | Idris, Mohd Yamani Idna |
| collection | UM |
| description | Shortest path algorithms are significant in graph theory and have been applied in many applications such as transportation and networking. Most of the shortest path calculation is performed on general purpose processor where instructions must be run to read the input, compute the result, and set the output which later on will slow down the overall performance. Therefore, the authors proposed a hardware approach which implements FPGA technology to find the shortest path between two nodes. The FPGA approach will demonstrate how parallelism can be used to significantly reduce calculation steps compared to sequential effort. In this paper, A-Star algorithm has been chosen for the shortest path calculation since it can achieve superior time running based on its heuristic behavior. |
| first_indexed | 2024-03-06T05:07:45Z |
| format | Conference or Workshop Item |
| id | um.eprints-2287 |
| institution | Universiti Malaya |
| last_indexed | 2024-03-06T05:07:45Z |
| publishDate | 2009 |
| record_format | dspace |
| spelling | um.eprints-22872019-02-07T04:42:52Z http://eprints.um.edu.my/2287/ High-Speed shortest path co-processor design Idris, Mohd Yamani Idna Abu Bakar, Suraya Tamil, Emran Mohd Razak, Zaidi Noor, Noorzaily Mohamed QA75 Electronic computers. Computer science Shortest path algorithms are significant in graph theory and have been applied in many applications such as transportation and networking. Most of the shortest path calculation is performed on general purpose processor where instructions must be run to read the input, compute the result, and set the output which later on will slow down the overall performance. Therefore, the authors proposed a hardware approach which implements FPGA technology to find the shortest path between two nodes. The FPGA approach will demonstrate how parallelism can be used to significantly reduce calculation steps compared to sequential effort. In this paper, A-Star algorithm has been chosen for the shortest path calculation since it can achieve superior time running based on its heuristic behavior. 2009 Conference or Workshop Item PeerReviewed Idris, Mohd Yamani Idna and Abu Bakar, Suraya and Tamil, Emran Mohd and Razak, Zaidi and Noor, Noorzaily Mohamed (2009) High-Speed shortest path co-processor design. In: 3rd Asia International Conference on Modelling and Simulation, 25-29 May 2009, Bali, Indonesia. https://ieeexplore.ieee.org/document/5072059 |
| spellingShingle | QA75 Electronic computers. Computer science Idris, Mohd Yamani Idna Abu Bakar, Suraya Tamil, Emran Mohd Razak, Zaidi Noor, Noorzaily Mohamed High-Speed shortest path co-processor design |
| title | High-Speed shortest path co-processor design |
| title_full | High-Speed shortest path co-processor design |
| title_fullStr | High-Speed shortest path co-processor design |
| title_full_unstemmed | High-Speed shortest path co-processor design |
| title_short | High-Speed shortest path co-processor design |
| title_sort | high speed shortest path co processor design |
| topic | QA75 Electronic computers. Computer science |
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