40 Gbit/s on-off-keyed system with 5.71 GHz clock recovery circuit using duty cycle division multiplexing
We show the realization of 40 Gbit/s on-off-keyed system that can be recovered at 5.71 GHz clock using duty cycle division multiplexing technique with the receiver sensitivity of -22.1 dBm. ©2008 Optical Society of America.
| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2009
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| Subjects: | |
| Online Access: | http://eprints.um.edu.my/6220/1/40_Gbits_on-off-keyed_system_with_5.71_GHz_clock_recovery_circuit_using_duty_cycle_division_multiplexing.pdf |