70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing
The performance of ASK over DCDM for up to seven channels is reported. The aggregate bit rate of 70 Gb/s is achieved with only 160-GHz modulation bandwidth. The clock and data recovery are realized at 10-GHz clock rate, which is very economic and efficient. At 7 � 10 Gb/s, the worst receiver sensit...
| Main Authors: | , , , , , , |
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| Format: | Article |
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Photonic Network Communications
2009
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| _version_ | 1796945412334026752 |
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| author | Amouzad Mahdiraji, G. Abdullah, M.K. Mokhtar, M. Mohammadi, A.M. Abas, A.F. Basir, S.M. Abdullah, R.S.A.R. |
| author_facet | Amouzad Mahdiraji, G. Abdullah, M.K. Mokhtar, M. Mohammadi, A.M. Abas, A.F. Basir, S.M. Abdullah, R.S.A.R. |
| author_sort | Amouzad Mahdiraji, G. |
| collection | UM |
| description | The performance of ASK over DCDM for up to seven channels is reported. The aggregate bit rate of 70 Gb/s is achieved with only 160-GHz modulation bandwidth. The clock and data recovery are realized at 10-GHz clock rate, which is very economic and efficient. At 7 � 10 Gb/s, the worst receiver sensitivity of�10 dBm, OSNR of 41.5 dB and chromatic dispersion tolerance of ±17 ps/nm are achieved. Whereas, for the best channel, the receiver sensitivity,OSNR, and chromatic dispersion tolerance are �23.5dBm, 29dB, and ±36 ps/nm, respectively. |
| first_indexed | 2024-03-06T05:16:15Z |
| format | Article |
| id | um.eprints-6221 |
| institution | Universiti Malaya |
| last_indexed | 2024-03-06T05:16:15Z |
| publishDate | 2009 |
| publisher | Photonic Network Communications |
| record_format | dspace |
| spelling | um.eprints-62212013-06-18T06:36:45Z http://eprints.um.edu.my/6221/ 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing Amouzad Mahdiraji, G. Abdullah, M.K. Mokhtar, M. Mohammadi, A.M. Abas, A.F. Basir, S.M. Abdullah, R.S.A.R. TA Engineering (General). Civil engineering (General) TK Electrical engineering. Electronics Nuclear engineering The performance of ASK over DCDM for up to seven channels is reported. The aggregate bit rate of 70 Gb/s is achieved with only 160-GHz modulation bandwidth. The clock and data recovery are realized at 10-GHz clock rate, which is very economic and efficient. At 7 � 10 Gb/s, the worst receiver sensitivity of�10 dBm, OSNR of 41.5 dB and chromatic dispersion tolerance of ±17 ps/nm are achieved. Whereas, for the best channel, the receiver sensitivity,OSNR, and chromatic dispersion tolerance are �23.5dBm, 29dB, and ±36 ps/nm, respectively. Photonic Network Communications 2009 Article PeerReviewed Amouzad Mahdiraji, G. and Abdullah, M.K. and Mokhtar, M. and Mohammadi, A.M. and Abas, A.F. and Basir, S.M. and Abdullah, R.S.A.R. (2009) 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing. Photonic Network Communications, 19 (3). pp. 233-239. ISSN 1572-8188, DOI https://doi.org/10.1007/s11107-009-0228-4 <https://doi.org/10.1007/s11107-009-0228-4>. http://download.springer.com/static/pdf/333/art%253A10.1007%252Fs11107-009-0228-4.pdf?auth66=1361235549_818caaac69cd5599ea81ec73fe253b52&ext=.pdf 10.1007/s11107-009-0228-4 |
| spellingShingle | TA Engineering (General). Civil engineering (General) TK Electrical engineering. Electronics Nuclear engineering Amouzad Mahdiraji, G. Abdullah, M.K. Mokhtar, M. Mohammadi, A.M. Abas, A.F. Basir, S.M. Abdullah, R.S.A.R. 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing |
| title | 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing |
| title_full | 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing |
| title_fullStr | 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing |
| title_full_unstemmed | 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing |
| title_short | 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing |
| title_sort | 70 gb s amplitude shift keyed system with 10 ghz clock recovery circuit using duty cycle division multiplexing |
| topic | TA Engineering (General). Civil engineering (General) TK Electrical engineering. Electronics Nuclear engineering |
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