Investigation on pattern based Algorithm for division by a constant number using Verilog code for optimization on the Nelust results
Even though sophisticated synthesis strategies are used for optimization (e.g. area and power consumption), the quality of the result heavily depends on the quality of the Register Transfer Level (RTL). For multiplication and division by a constant number that is power of 2 can be done using left sh...
Päätekijät: | Fouziah Md Yassin, Ag Asri Ag Ibrahim, Zaturrawiah Ali Omar, Saturi Baco |
---|---|
Aineistotyyppi: | Research Report |
Kieli: | English |
Julkaistu: |
Universiti Malaysia Sabah
2015
|
Aiheet: | |
Linkit: | https://eprints.ums.edu.my/id/eprint/22892/1/Investigation%20on%20pattern%20based%20Algorithm%20for%20division%20by%20a%20constant%20number%20using%20Verilog%20code%20for%20optimization%20on%20the%20Nelust%20results.pdf |
Samankaltaisia teoksia
-
Rounded off unsigned constant division using add-shift in verilog
Tekijä: Fouziah Md Yassin, et al.
Julkaistu: (2016) -
Facial Expression Effect on Signal Quality and the Attention Level of Mind wave
Tekijä: Fouziah Md Yassin, et al.
Julkaistu: (2021) -
The effect of color on the attention level
Tekijä: Fouziah Md Yassin, et al.
Julkaistu: (2021) -
Colours Effect Analysis on The Attention Level with A Single-Channel EEG
Tekijä: Fouziah Md Yassin, et al.
Julkaistu: (2022) -
Power Added Efficiency Model for Mesfet Class E Power Amplifier Using Jackknife Resampling
Tekijä: Fouziah Md. Yassin, et al.
Julkaistu: (2013)