ASIC Layout Design-Space Exploration of Pan-and-Tompkins Pre-Processing Algorithm for High Efficiency Electrocardiogram Monitor
Cardiovascular diseases (CVDs) is the leading cause of the death globally. Ambulatory Electrocardiogram (ECG) and mobile monitoring is very important for early heart disease detection and prevention, but its measurement normally contains various types of noise which affect the analysis accuracy. Mor...
| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Language: | English English |
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2020
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| Online Access: | https://eprints.ums.edu.my/id/eprint/30451/1/ASIC%20Layout%20Design-Space%20Exploration%20of%20Pan-and-Tompkins%20Pre-Processing%20Algorithm%20for%20High%20Efficiency%20Electrocardiogram%20Monitor%20abstract%20.pdf https://eprints.ums.edu.my/id/eprint/30451/2/ASIC%20Layout%20Design-Space%20Exploration%20of%20Pan-and-Tompkins%20Pre-Processing%20Algorithm%20for%20High%20Efficiency%20Electrocardiogram%20Monitor.pdf |
| _version_ | 1825714357405745152 |
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| author | Jia, Hui Lim Yuan, Wen Hau Hoe, Tung Yew Sreedharan Baskara Dass |
| author_facet | Jia, Hui Lim Yuan, Wen Hau Hoe, Tung Yew Sreedharan Baskara Dass |
| author_sort | Jia, Hui Lim |
| collection | UMS |
| description | Cardiovascular diseases (CVDs) is the leading cause of the death globally. Ambulatory Electrocardiogram (ECG) and mobile monitoring is very important for early heart disease detection and prevention, but its measurement normally contains various types of noise which affect the analysis accuracy. Moreover, long hour ECG monitoring requires an efficient architecture to support real-time processing and low power consumption. This paper presents an application specific integrated circuit (ASIC) design of Pan-and-Tompkins ECG pre-processing algorithm which aims to remove several unwanted noise to increase analysis accuracy. The complete design flow covers high-level algorithm modelling in Matlab, followed by synthesizable design at Register Transfer Level (RTL) until logic synthesis, physical synthesis and static timing analysis to produce VLSI layout. Several power optimization techniques as well as different ASIC process technology libraries in terms of SilTerra’s 180nm CMOS Logic Generic Library (CL180G) and Synopsys 32nm Generic Library (SAED32) are deployed for design-space exploration to study the design trade-off in terms of power consumption, timing performance, and the logic area usage. Results show that the clock gating technique is able to reduce 32.4% of dynamic power in design using CL180G generic library, whereas the integration of several power optimization techniques using SAED32 generic library is able to reduce 43.82% of dynamic power, 91.21% of leakage power and 91.25% of total power. |
| first_indexed | 2024-03-06T03:10:37Z |
| format | Conference or Workshop Item |
| id | ums.eprints-30451 |
| institution | Universiti Malaysia Sabah |
| language | English English |
| last_indexed | 2024-03-06T03:10:37Z |
| publishDate | 2020 |
| record_format | dspace |
| spelling | ums.eprints-304512021-09-06T05:38:37Z https://eprints.ums.edu.my/id/eprint/30451/ ASIC Layout Design-Space Exploration of Pan-and-Tompkins Pre-Processing Algorithm for High Efficiency Electrocardiogram Monitor Jia, Hui Lim Yuan, Wen Hau Hoe, Tung Yew Sreedharan Baskara Dass TK7885-7895 Computer engineering. Computer hardware Cardiovascular diseases (CVDs) is the leading cause of the death globally. Ambulatory Electrocardiogram (ECG) and mobile monitoring is very important for early heart disease detection and prevention, but its measurement normally contains various types of noise which affect the analysis accuracy. Moreover, long hour ECG monitoring requires an efficient architecture to support real-time processing and low power consumption. This paper presents an application specific integrated circuit (ASIC) design of Pan-and-Tompkins ECG pre-processing algorithm which aims to remove several unwanted noise to increase analysis accuracy. The complete design flow covers high-level algorithm modelling in Matlab, followed by synthesizable design at Register Transfer Level (RTL) until logic synthesis, physical synthesis and static timing analysis to produce VLSI layout. Several power optimization techniques as well as different ASIC process technology libraries in terms of SilTerra’s 180nm CMOS Logic Generic Library (CL180G) and Synopsys 32nm Generic Library (SAED32) are deployed for design-space exploration to study the design trade-off in terms of power consumption, timing performance, and the logic area usage. Results show that the clock gating technique is able to reduce 32.4% of dynamic power in design using CL180G generic library, whereas the integration of several power optimization techniques using SAED32 generic library is able to reduce 43.82% of dynamic power, 91.21% of leakage power and 91.25% of total power. 2020 Conference or Workshop Item NonPeerReviewed text en https://eprints.ums.edu.my/id/eprint/30451/1/ASIC%20Layout%20Design-Space%20Exploration%20of%20Pan-and-Tompkins%20Pre-Processing%20Algorithm%20for%20High%20Efficiency%20Electrocardiogram%20Monitor%20abstract%20.pdf text en https://eprints.ums.edu.my/id/eprint/30451/2/ASIC%20Layout%20Design-Space%20Exploration%20of%20Pan-and-Tompkins%20Pre-Processing%20Algorithm%20for%20High%20Efficiency%20Electrocardiogram%20Monitor.pdf Jia, Hui Lim and Yuan, Wen Hau and Hoe, Tung Yew and Sreedharan Baskara Dass (2020) ASIC Layout Design-Space Exploration of Pan-and-Tompkins Pre-Processing Algorithm for High Efficiency Electrocardiogram Monitor. In: 2020 IEEE 2nd International Conference on Artificial Intelligence in Engineering and Technology (IICAIET), 20 November 2020, Kota Kinabalu, Malaysia. (Submitted) https://ieeexplore.ieee.org/document/9257862 |
| spellingShingle | TK7885-7895 Computer engineering. Computer hardware Jia, Hui Lim Yuan, Wen Hau Hoe, Tung Yew Sreedharan Baskara Dass ASIC Layout Design-Space Exploration of Pan-and-Tompkins Pre-Processing Algorithm for High Efficiency Electrocardiogram Monitor |
| title | ASIC Layout Design-Space Exploration of Pan-and-Tompkins Pre-Processing Algorithm for High Efficiency Electrocardiogram Monitor |
| title_full | ASIC Layout Design-Space Exploration of Pan-and-Tompkins Pre-Processing Algorithm for High Efficiency Electrocardiogram Monitor |
| title_fullStr | ASIC Layout Design-Space Exploration of Pan-and-Tompkins Pre-Processing Algorithm for High Efficiency Electrocardiogram Monitor |
| title_full_unstemmed | ASIC Layout Design-Space Exploration of Pan-and-Tompkins Pre-Processing Algorithm for High Efficiency Electrocardiogram Monitor |
| title_short | ASIC Layout Design-Space Exploration of Pan-and-Tompkins Pre-Processing Algorithm for High Efficiency Electrocardiogram Monitor |
| title_sort | asic layout design space exploration of pan and tompkins pre processing algorithm for high efficiency electrocardiogram monitor |
| topic | TK7885-7895 Computer engineering. Computer hardware |
| url | https://eprints.ums.edu.my/id/eprint/30451/1/ASIC%20Layout%20Design-Space%20Exploration%20of%20Pan-and-Tompkins%20Pre-Processing%20Algorithm%20for%20High%20Efficiency%20Electrocardiogram%20Monitor%20abstract%20.pdf https://eprints.ums.edu.my/id/eprint/30451/2/ASIC%20Layout%20Design-Space%20Exploration%20of%20Pan-and-Tompkins%20Pre-Processing%20Algorithm%20for%20High%20Efficiency%20Electrocardiogram%20Monitor.pdf |
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