Energy-performance optimization via P/N ratio sizing with full diffusion layout structure and standard cell height tuning in near-threshold voltage operation
In recent decades, near-threshold voltage (NTV) design has become a well-known technique for improving the energy efficiency of digital integrated circuits. However, scaling down the operating voltage to the NTV raises two major challenges for robust operation: process variability and performance de...
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Published: |
IEEE
2022
|
| _version_ | 1817927499385929728 |
|---|---|
| author | Lim, Yang Wei Kamsani, Noor Ain Mohd Sidek, Roslina Hashim, Shaiful Jahari Rokhani, Fakhrul Zaman |
| author_facet | Lim, Yang Wei Kamsani, Noor Ain Mohd Sidek, Roslina Hashim, Shaiful Jahari Rokhani, Fakhrul Zaman |
| author_sort | Lim, Yang Wei |
| collection | UPM |
| description | In recent decades, near-threshold voltage (NTV) design has become a well-known technique for improving the energy efficiency of digital integrated circuits. However, scaling down the operating voltage to the NTV raises two major challenges for robust operation: process variability and performance degradation. In this study, we propose a joint optimization technique for standard cell design to address the challenge of performance degradation in NTV design. The standard cell P/N ratio (PMOS width to NMOS width ratio) is being sized to maximize the performance with the constraint of a full diffusion (FD) layout structure, and the standard cell height is jointly optimized to further improve the circuits performance or energy consumption. Increasing the standard cell height improves the circuit performance at the cost of higher energy consumption, whereas lowering the standard cell height sacrifices the circuits performance for better energy saving. The results showed that implementing the taller library (14-track) in an AMBA high-speed bus (AHB) controller circuit can improve performance by up to 4.5. The shortest library (7-track) resulted in 55 energy savings in the same circuit implementation. The test chip fabricated in 110-nm CMOS technology demonstrated successful operation of 8051 microcontroller down to 0.6V with the custom-designed 7-track library. The measurement results showed 4.3X energy saving compared to the operation at a supply voltage of 1.2V. |
| first_indexed | 2024-12-09T02:19:25Z |
| format | Article |
| id | upm.eprints-107683 |
| institution | Universiti Putra Malaysia |
| last_indexed | 2024-12-09T02:19:25Z |
| publishDate | 2022 |
| publisher | IEEE |
| record_format | dspace |
| spelling | upm.eprints-1076832024-10-07T01:51:51Z http://psasir.upm.edu.my/id/eprint/107683/ Energy-performance optimization via P/N ratio sizing with full diffusion layout structure and standard cell height tuning in near-threshold voltage operation Lim, Yang Wei Kamsani, Noor Ain Mohd Sidek, Roslina Hashim, Shaiful Jahari Rokhani, Fakhrul Zaman In recent decades, near-threshold voltage (NTV) design has become a well-known technique for improving the energy efficiency of digital integrated circuits. However, scaling down the operating voltage to the NTV raises two major challenges for robust operation: process variability and performance degradation. In this study, we propose a joint optimization technique for standard cell design to address the challenge of performance degradation in NTV design. The standard cell P/N ratio (PMOS width to NMOS width ratio) is being sized to maximize the performance with the constraint of a full diffusion (FD) layout structure, and the standard cell height is jointly optimized to further improve the circuits performance or energy consumption. Increasing the standard cell height improves the circuit performance at the cost of higher energy consumption, whereas lowering the standard cell height sacrifices the circuits performance for better energy saving. The results showed that implementing the taller library (14-track) in an AMBA high-speed bus (AHB) controller circuit can improve performance by up to 4.5. The shortest library (7-track) resulted in 55 energy savings in the same circuit implementation. The test chip fabricated in 110-nm CMOS technology demonstrated successful operation of 8051 microcontroller down to 0.6V with the custom-designed 7-track library. The measurement results showed 4.3X energy saving compared to the operation at a supply voltage of 1.2V. IEEE 2022-12-20 Article PeerReviewed Lim, Yang Wei and Kamsani, Noor Ain and Mohd Sidek, Roslina and Hashim, Shaiful Jahari and Rokhani, Fakhrul Zaman (2022) Energy-performance optimization via P/N ratio sizing with full diffusion layout structure and standard cell height tuning in near-threshold voltage operation. IEEE Access, 11. pp. 12536-12546. ISSN 2169-3536 https://ieeexplore.ieee.org/document/9994729/ 10.1109/access.2022.3230897 |
| spellingShingle | Lim, Yang Wei Kamsani, Noor Ain Mohd Sidek, Roslina Hashim, Shaiful Jahari Rokhani, Fakhrul Zaman Energy-performance optimization via P/N ratio sizing with full diffusion layout structure and standard cell height tuning in near-threshold voltage operation |
| title | Energy-performance optimization via P/N ratio sizing with full diffusion layout structure and standard cell height tuning in near-threshold voltage operation |
| title_full | Energy-performance optimization via P/N ratio sizing with full diffusion layout structure and standard cell height tuning in near-threshold voltage operation |
| title_fullStr | Energy-performance optimization via P/N ratio sizing with full diffusion layout structure and standard cell height tuning in near-threshold voltage operation |
| title_full_unstemmed | Energy-performance optimization via P/N ratio sizing with full diffusion layout structure and standard cell height tuning in near-threshold voltage operation |
| title_short | Energy-performance optimization via P/N ratio sizing with full diffusion layout structure and standard cell height tuning in near-threshold voltage operation |
| title_sort | energy performance optimization via p n ratio sizing with full diffusion layout structure and standard cell height tuning in near threshold voltage operation |
| work_keys_str_mv | AT limyangwei energyperformanceoptimizationviapnratiosizingwithfulldiffusionlayoutstructureandstandardcellheighttuninginnearthresholdvoltageoperation AT kamsaninoorain energyperformanceoptimizationviapnratiosizingwithfulldiffusionlayoutstructureandstandardcellheighttuninginnearthresholdvoltageoperation AT mohdsidekroslina energyperformanceoptimizationviapnratiosizingwithfulldiffusionlayoutstructureandstandardcellheighttuninginnearthresholdvoltageoperation AT hashimshaifuljahari energyperformanceoptimizationviapnratiosizingwithfulldiffusionlayoutstructureandstandardcellheighttuninginnearthresholdvoltageoperation AT rokhanifakhrulzaman energyperformanceoptimizationviapnratiosizingwithfulldiffusionlayoutstructureandstandardcellheighttuninginnearthresholdvoltageoperation |