70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing
The performance of ASK over DCDM for up to seven channels is reported. The aggregate bit rate of 70 Gb/s is achieved with only 160-GHz modulation bandwidth. The clock and data recovery are realized at 10-GHz clock rate, which is very economic and efficient. At 7 × 10 Gb/s, the worst receiver sensiti...
| Main Authors: | , , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Springer
2010
|
| Online Access: | http://psasir.upm.edu.my/id/eprint/11439/1/70.pdf |
| _version_ | 1796968087367450624 |
|---|---|
| author | Mahdiraji, Ghafour Amouzad Abdullah, Mohamad Khazani Mokhtar, Makhfudzah Mohammadi, Amin Malek Abas, Ahmad Fauzi Mohd Basir, Safuraa Raja Abdullah, Raja Syamsul Azmir |
| author_facet | Mahdiraji, Ghafour Amouzad Abdullah, Mohamad Khazani Mokhtar, Makhfudzah Mohammadi, Amin Malek Abas, Ahmad Fauzi Mohd Basir, Safuraa Raja Abdullah, Raja Syamsul Azmir |
| author_sort | Mahdiraji, Ghafour Amouzad |
| collection | UPM |
| description | The performance of ASK over DCDM for up to seven channels is reported. The aggregate bit rate of 70 Gb/s is achieved with only 160-GHz modulation bandwidth. The clock and data recovery are realized at 10-GHz clock rate, which is very economic and efficient. At 7 × 10 Gb/s, the worst receiver sensitivity of −10 dBm, OSNR of 41.5 dB and chromatic dispersion tolerance of ±7 ps/nm are achieved. Whereas, for the best channel, the receiver sensitivity, OSNR, and chromatic dispersion tolerance are −23.5 dBm, 29 dB, and ±36 ps/nm, respectively. |
| first_indexed | 2024-03-06T07:23:17Z |
| format | Article |
| id | upm.eprints-11439 |
| institution | Universiti Putra Malaysia |
| language | English |
| last_indexed | 2024-03-06T07:23:17Z |
| publishDate | 2010 |
| publisher | Springer |
| record_format | dspace |
| spelling | upm.eprints-114392016-09-30T01:17:03Z http://psasir.upm.edu.my/id/eprint/11439/ 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing Mahdiraji, Ghafour Amouzad Abdullah, Mohamad Khazani Mokhtar, Makhfudzah Mohammadi, Amin Malek Abas, Ahmad Fauzi Mohd Basir, Safuraa Raja Abdullah, Raja Syamsul Azmir The performance of ASK over DCDM for up to seven channels is reported. The aggregate bit rate of 70 Gb/s is achieved with only 160-GHz modulation bandwidth. The clock and data recovery are realized at 10-GHz clock rate, which is very economic and efficient. At 7 × 10 Gb/s, the worst receiver sensitivity of −10 dBm, OSNR of 41.5 dB and chromatic dispersion tolerance of ±7 ps/nm are achieved. Whereas, for the best channel, the receiver sensitivity, OSNR, and chromatic dispersion tolerance are −23.5 dBm, 29 dB, and ±36 ps/nm, respectively. Springer 2010 Article PeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/11439/1/70.pdf Mahdiraji, Ghafour Amouzad and Abdullah, Mohamad Khazani and Mokhtar, Makhfudzah and Mohammadi, Amin Malek and Abas, Ahmad Fauzi and Mohd Basir, Safuraa and Raja Abdullah, Raja Syamsul Azmir (2010) 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing. Photonic Network Communications, 19 (3). pp. 233-239. ISSN 1387-974X; ESSN: 1572-8188 http://link.springer.com/article/10.1007/s11107-009-0228-4?view=classic 10.1007/s11107-009-0228-4 |
| spellingShingle | Mahdiraji, Ghafour Amouzad Abdullah, Mohamad Khazani Mokhtar, Makhfudzah Mohammadi, Amin Malek Abas, Ahmad Fauzi Mohd Basir, Safuraa Raja Abdullah, Raja Syamsul Azmir 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing |
| title | 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing |
| title_full | 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing |
| title_fullStr | 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing |
| title_full_unstemmed | 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing |
| title_short | 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing |
| title_sort | 70 gb s amplitude shift keyed system with 10 ghz clock recovery circuit using duty cycle division multiplexing |
| url | http://psasir.upm.edu.my/id/eprint/11439/1/70.pdf |
| work_keys_str_mv | AT mahdirajighafouramouzad 70gbsamplitudeshiftkeyedsystemwith10ghzclockrecoverycircuitusingdutycycledivisionmultiplexing AT abdullahmohamadkhazani 70gbsamplitudeshiftkeyedsystemwith10ghzclockrecoverycircuitusingdutycycledivisionmultiplexing AT mokhtarmakhfudzah 70gbsamplitudeshiftkeyedsystemwith10ghzclockrecoverycircuitusingdutycycledivisionmultiplexing AT mohammadiaminmalek 70gbsamplitudeshiftkeyedsystemwith10ghzclockrecoverycircuitusingdutycycledivisionmultiplexing AT abasahmadfauzi 70gbsamplitudeshiftkeyedsystemwith10ghzclockrecoverycircuitusingdutycycledivisionmultiplexing AT mohdbasirsafuraa 70gbsamplitudeshiftkeyedsystemwith10ghzclockrecoverycircuitusingdutycycledivisionmultiplexing AT rajaabdullahrajasyamsulazmir 70gbsamplitudeshiftkeyedsystemwith10ghzclockrecoverycircuitusingdutycycledivisionmultiplexing |