Area efficient test circuit for library standard cell qualification
High cost of qualifying library standard cells on silicon wafer limits the number of test circuits on the test chip. This paper proposes a technique to share common load circuits among test circuits to reduce the silicon area. By enabling the load sharing, number of transistors for the common load c...
| Hoofdauteurs: | , , , , |
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| Formaat: | Conference or Workshop Item |
| Taal: | English |
| Gepubliceerd in: |
IEEE
2015
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| Online toegang: | http://psasir.upm.edu.my/id/eprint/2848/1/Area%20efficient%20test%20circuit%20for%20library%20standard%20cell%20qualification.pdf |
| _version_ | 1825921540696309760 |
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| author | Al-Frajat, Jaafar Khadair Kadam Flayyih, Wameedh Nazar Mohd Sidek, Roslina Samsudin, Khairulmizam Rokhani, Fakhrul Zaman |
| author_facet | Al-Frajat, Jaafar Khadair Kadam Flayyih, Wameedh Nazar Mohd Sidek, Roslina Samsudin, Khairulmizam Rokhani, Fakhrul Zaman |
| author_sort | Al-Frajat, Jaafar Khadair Kadam |
| collection | UPM |
| description | High cost of qualifying library standard cells on silicon wafer limits the number of test circuits on the test chip. This paper proposes a technique to share common load circuits among test circuits to reduce the silicon area. By enabling the load sharing, number of transistors for the common load can be reduced significantly. Results show up to 80% reduction in silicon area due to load area reduction. |
| first_indexed | 2024-03-06T06:59:24Z |
| format | Conference or Workshop Item |
| id | upm.eprints-2848 |
| institution | Universiti Putra Malaysia |
| language | English |
| last_indexed | 2024-03-06T06:59:24Z |
| publishDate | 2015 |
| publisher | IEEE |
| record_format | dspace |
| spelling | upm.eprints-28482018-01-15T09:08:15Z http://psasir.upm.edu.my/id/eprint/2848/ Area efficient test circuit for library standard cell qualification Al-Frajat, Jaafar Khadair Kadam Flayyih, Wameedh Nazar Mohd Sidek, Roslina Samsudin, Khairulmizam Rokhani, Fakhrul Zaman High cost of qualifying library standard cells on silicon wafer limits the number of test circuits on the test chip. This paper proposes a technique to share common load circuits among test circuits to reduce the silicon area. By enabling the load sharing, number of transistors for the common load can be reduced significantly. Results show up to 80% reduction in silicon area due to load area reduction. IEEE 2015 Conference or Workshop Item PeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/2848/1/Area%20efficient%20test%20circuit%20for%20library%20standard%20cell%20qualification.pdf Al-Frajat, Jaafar Khadair Kadam and Flayyih, Wameedh Nazar and Mohd Sidek, Roslina and Samsudin, Khairulmizam and Rokhani, Fakhrul Zaman (2015) Area efficient test circuit for library standard cell qualification. In: 5th International Conference on Energy Aware Computing Systems & Applications (ICEAC 2015), 24-26 Mar. 2015, Cairo, Egypt. . 10.1109/ICEAC.2015.7352210 |
| spellingShingle | Al-Frajat, Jaafar Khadair Kadam Flayyih, Wameedh Nazar Mohd Sidek, Roslina Samsudin, Khairulmizam Rokhani, Fakhrul Zaman Area efficient test circuit for library standard cell qualification |
| title | Area efficient test circuit for library standard cell qualification |
| title_full | Area efficient test circuit for library standard cell qualification |
| title_fullStr | Area efficient test circuit for library standard cell qualification |
| title_full_unstemmed | Area efficient test circuit for library standard cell qualification |
| title_short | Area efficient test circuit for library standard cell qualification |
| title_sort | area efficient test circuit for library standard cell qualification |
| url | http://psasir.upm.edu.my/id/eprint/2848/1/Area%20efficient%20test%20circuit%20for%20library%20standard%20cell%20qualification.pdf |
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