Fabrication and simulation of lithographically defined junctionless lateral gate silicon nanowire transistors
Nowadays most of the industrial technology in fabrication of transistors is based on the use of semiconductor junctions. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms in the semiconductor, the formation of ultra-shallow junctions with high doping...
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| Format: | Thesis |
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2012
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| _version_ | 1796972359657193472 |
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| author | Larki, Farhad |
| author_facet | Larki, Farhad |
| author_sort | Larki, Farhad |
| collection | UPM |
| description | Nowadays most of the industrial technology in fabrication of transistors is based on the use of semiconductor junctions. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms in the semiconductor, the formation of ultra-shallow junctions with high doping concentration gradients has become an increasingly difficult challenge for the semiconductor industry. Thus, scaling-down of semiconductor devices, which remarkably follows Moore's law during the last 40 years, has pushed complementary metal–oxide–semiconductor (CMOS) devices close to fundamental limits. In order to keep the validity of Moore's law, device down scaling is not enough. So called material and geometry technology boosters have been introduced. High-k dielectrics, silicon-on-insulator substrates or strained silicon are some booster examples that were used at sub-micron scale.
In this work, unconventional technique of atomic force microscopy (AFM) nanolithography via local anodic oxidation process was performed to fabricate junctionless lateral gate silicon nanowire transistors (JLGSNWTs) which have no
physical junction and no dielectric material. We have chosen to use the oxidation by AFM in contact mode. This process was applied to a lightly doped (1015 cm−3) p-type
(100) silicon on insulator (SOI) wafer with top silicon thickness of 100 nm and a 200 nm buried oxide (BOX) thickness with a resistivity of 13.5–22.5 Ω cm. Modified RCA
cleaning process and hydrofluoric acid (HF) etching used in order to prepare the sample for further fabrication steps. By examining different voltage bias ranging from 3-10 V,
writing speed ranging from 0.1-10 μm/s, and different environmental condition (temperature and humidity), we optimized the fabrication parameters. Applying a 9 V
voltage to a Cr/Pt tip, while it was scanning once over the silicon surface at speed of 1 μm/s, led to a 2–3 nm-thick oxide pattern of width 80–90 nm which was the smallest
reproducible dimensions achieved. Humidity was maintained in the range of 55%-68%. An anisotropic wet chemical etching process was performed to remove uncovered
portion of the structure. Solutions of 30 and 40 wt% Potassium Hydroxide (KOH), saturated with isopropyl alcohol (IPA) at the temperature range of 60 - 80 were used to remove all the non protected silicon areas. The best results achieved are at 30 wt% and 65 . The electrical characteristics of the JLGSNWTs were measured by an
HP4156C semiconductor parameter analyzer (SPA, Agilent) at room temperature. The device showed the characteristic similar to normal MOSFET; however the principle of operation is completely different. The output characteristics of the fabricated device with 100 nm nanowire width, 100 nm nanowire thickness, 4.2 μm nanowire length, and 100 nm gate gap shows an ION/IOFF ratio in the order of 105.
Since the device structure was new and operational principle of transistor was not clear, thus, the same structure was simulated using Technology Computer-Aided Design (TCAD). In order to do, Sentaurus software tool is used as the platform for the 3D TCAD simulation. The output characteristic has been compared with the experimental
results and critical physical quantities such as carries density, electric field configuration, carriers‘ recombination-generation possibility, and carriers‘ mobility
which affects the characteristics of the device has been carefully investigated. The analysis of the extracted parameters from the simulation revealed that the JLGSNWTs
are normally on devices which by applying positive voltage to the lateral gates turn the devices off based on the pinch off mechanism, but increasing negative gate voltages
were not able to improve the current significantly. The saturation current is proportional to the device cross width, thickness, the channel length, the semiconductor nanowire doping density, and a voltage which obeying Vch ≤ Vds, and not to the gate capacitance.
In addition, devices which from technical point of view were difficult or too expensive to be fabricated have been investigated by simulation process. Effect of nanowire length (S/D distance), channel length (area under the gate), nanowire width, nanowire thickness, and gate gap on behavior of device has been investigated. It has been observed that decreasing the nanowire length increases the output current due to the change in electric field configuration in the gates position from 2.0 10 3 V.cm-1 for a device with 4.2 μm nanowire length to 6.0 x 103 V.cm-1 for a device with 1 μm nanowire length. Channel length was more effective when the positive gate voltage applied to the lateral gates. The ION/IOFF varies from 102 for device with 50 nm channel length to 109 for device with 400 nm channel length. Because of the symmetry of the structures the effect of channel width and channel thickness was quite the same. The narrower and thinner structures presented lower off current and better control of gates on the behavior of carriers. The gate gap is another parameter which affected the behavior of the device due to the change of electric field magnitude which directly
affect carriers‘ density and mobility of the carriers. |
| first_indexed | 2024-03-06T08:26:51Z |
| format | Thesis |
| id | upm.eprints-33674 |
| institution | Universiti Putra Malaysia |
| last_indexed | 2024-03-06T08:26:51Z |
| publishDate | 2012 |
| record_format | dspace |
| spelling | upm.eprints-336742015-03-12T01:18:04Z http://psasir.upm.edu.my/id/eprint/33674/ Fabrication and simulation of lithographically defined junctionless lateral gate silicon nanowire transistors Larki, Farhad Nowadays most of the industrial technology in fabrication of transistors is based on the use of semiconductor junctions. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms in the semiconductor, the formation of ultra-shallow junctions with high doping concentration gradients has become an increasingly difficult challenge for the semiconductor industry. Thus, scaling-down of semiconductor devices, which remarkably follows Moore's law during the last 40 years, has pushed complementary metal–oxide–semiconductor (CMOS) devices close to fundamental limits. In order to keep the validity of Moore's law, device down scaling is not enough. So called material and geometry technology boosters have been introduced. High-k dielectrics, silicon-on-insulator substrates or strained silicon are some booster examples that were used at sub-micron scale. In this work, unconventional technique of atomic force microscopy (AFM) nanolithography via local anodic oxidation process was performed to fabricate junctionless lateral gate silicon nanowire transistors (JLGSNWTs) which have no physical junction and no dielectric material. We have chosen to use the oxidation by AFM in contact mode. This process was applied to a lightly doped (1015 cm−3) p-type (100) silicon on insulator (SOI) wafer with top silicon thickness of 100 nm and a 200 nm buried oxide (BOX) thickness with a resistivity of 13.5–22.5 Ω cm. Modified RCA cleaning process and hydrofluoric acid (HF) etching used in order to prepare the sample for further fabrication steps. By examining different voltage bias ranging from 3-10 V, writing speed ranging from 0.1-10 μm/s, and different environmental condition (temperature and humidity), we optimized the fabrication parameters. Applying a 9 V voltage to a Cr/Pt tip, while it was scanning once over the silicon surface at speed of 1 μm/s, led to a 2–3 nm-thick oxide pattern of width 80–90 nm which was the smallest reproducible dimensions achieved. Humidity was maintained in the range of 55%-68%. An anisotropic wet chemical etching process was performed to remove uncovered portion of the structure. Solutions of 30 and 40 wt% Potassium Hydroxide (KOH), saturated with isopropyl alcohol (IPA) at the temperature range of 60 - 80 were used to remove all the non protected silicon areas. The best results achieved are at 30 wt% and 65 . The electrical characteristics of the JLGSNWTs were measured by an HP4156C semiconductor parameter analyzer (SPA, Agilent) at room temperature. The device showed the characteristic similar to normal MOSFET; however the principle of operation is completely different. The output characteristics of the fabricated device with 100 nm nanowire width, 100 nm nanowire thickness, 4.2 μm nanowire length, and 100 nm gate gap shows an ION/IOFF ratio in the order of 105. Since the device structure was new and operational principle of transistor was not clear, thus, the same structure was simulated using Technology Computer-Aided Design (TCAD). In order to do, Sentaurus software tool is used as the platform for the 3D TCAD simulation. The output characteristic has been compared with the experimental results and critical physical quantities such as carries density, electric field configuration, carriers‘ recombination-generation possibility, and carriers‘ mobility which affects the characteristics of the device has been carefully investigated. The analysis of the extracted parameters from the simulation revealed that the JLGSNWTs are normally on devices which by applying positive voltage to the lateral gates turn the devices off based on the pinch off mechanism, but increasing negative gate voltages were not able to improve the current significantly. The saturation current is proportional to the device cross width, thickness, the channel length, the semiconductor nanowire doping density, and a voltage which obeying Vch ≤ Vds, and not to the gate capacitance. In addition, devices which from technical point of view were difficult or too expensive to be fabricated have been investigated by simulation process. Effect of nanowire length (S/D distance), channel length (area under the gate), nanowire width, nanowire thickness, and gate gap on behavior of device has been investigated. It has been observed that decreasing the nanowire length increases the output current due to the change in electric field configuration in the gates position from 2.0 10 3 V.cm-1 for a device with 4.2 μm nanowire length to 6.0 x 103 V.cm-1 for a device with 1 μm nanowire length. Channel length was more effective when the positive gate voltage applied to the lateral gates. The ION/IOFF varies from 102 for device with 50 nm channel length to 109 for device with 400 nm channel length. Because of the symmetry of the structures the effect of channel width and channel thickness was quite the same. The narrower and thinner structures presented lower off current and better control of gates on the behavior of carriers. The gate gap is another parameter which affected the behavior of the device due to the change of electric field magnitude which directly affect carriers‘ density and mobility of the carriers. 2012-12 Thesis NonPeerReviewed Larki, Farhad (2012) Fabrication and simulation of lithographically defined junctionless lateral gate silicon nanowire transistors. PhD thesis, Universiti Putra Malaysia. Lithography Transistors Nanolithography |
| spellingShingle | Lithography Transistors Nanolithography Larki, Farhad Fabrication and simulation of lithographically defined junctionless lateral gate silicon nanowire transistors |
| title | Fabrication and simulation of lithographically defined junctionless lateral gate silicon nanowire transistors |
| title_full | Fabrication and simulation of lithographically defined junctionless lateral gate silicon nanowire transistors |
| title_fullStr | Fabrication and simulation of lithographically defined junctionless lateral gate silicon nanowire transistors |
| title_full_unstemmed | Fabrication and simulation of lithographically defined junctionless lateral gate silicon nanowire transistors |
| title_short | Fabrication and simulation of lithographically defined junctionless lateral gate silicon nanowire transistors |
| title_sort | fabrication and simulation of lithographically defined junctionless lateral gate silicon nanowire transistors |
| topic | Lithography Transistors Nanolithography |
| work_keys_str_mv | AT larkifarhad fabricationandsimulationoflithographicallydefinedjunctionlesslateralgatesiliconnanowiretransistors |