Analysis and modeling of ASIC area at early-stage design for standard cell library selection
Area-delay curve is an effective technique to compare and select the appropriate library at different target delay constraint. However, generating area-delay curve requires time-consuming synthesis processes. This paper presents a fast area estimation model to allow the designer to select the optima...
| المؤلفون الرئيسيون: | , , , , |
|---|---|
| التنسيق: | Conference or Workshop Item |
| اللغة: | English |
| منشور في: |
IEEE
2019
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| الوصول للمادة أونلاين: | http://psasir.upm.edu.my/id/eprint/36345/1/Analysis%20and%20modeling%20of%20ASIC%20area%20at%20early-stage%20design%20for%20standard%20cell%20library%20selection.pdf |