A survey of on-chip monitors
Systems on Chips (SoCs) architecture complexity is result of integrating a large numbers of cores in a single chip. The approaches should address the systems particular challenges such as reliability, performance, and power constraints. Monitoring became a necessary part for testing, debugging...
| Main Authors: | , , , , |
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| Format: | Conference or Workshop Item |
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IEEE
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| _version_ | 1796973500270903296 |
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| author | Rahimipour, S. Rokhani, Fakhrul Zaman Shafie, Suhaidi El-Azhary, I. Flayyih, W.N. |
| author_facet | Rahimipour, S. Rokhani, Fakhrul Zaman Shafie, Suhaidi El-Azhary, I. Flayyih, W.N. |
| author_sort | Rahimipour, S. |
| collection | UPM |
| description | Systems on Chips (SoCs) architecture complexity
is result of integrating a large numbers of cores in
a single chip. The approaches should address the systems
particular challenges such as reliability, performance, and
power constraints. Monitoring became a necessary part
for testing, debugging and performance evaluations of
SoCs at run time, as On-chip monitoring is employed to
provide environmental information, such as temperature,
voltage, and error data. Real-time system validation is
done by exploiting the monitoring to determine the proper
operation of a system within the designed parameters. The
paper explains the common monitoring operations in SoCs,
showing the functionality of thermal, voltage and soft error
monitors. The different architectures that are approached
by the research community until now are discussed. |
| first_indexed | 2024-03-06T08:43:34Z |
| format | Conference or Workshop Item |
| id | upm.eprints-39236 |
| institution | Universiti Putra Malaysia |
| last_indexed | 2024-03-06T08:43:34Z |
| publisher | IEEE |
| record_format | dspace |
| spelling | upm.eprints-392362015-07-10T08:49:18Z http://psasir.upm.edu.my/id/eprint/39236/ A survey of on-chip monitors Rahimipour, S. Rokhani, Fakhrul Zaman Shafie, Suhaidi El-Azhary, I. Flayyih, W.N. Systems on Chips (SoCs) architecture complexity is result of integrating a large numbers of cores in a single chip. The approaches should address the systems particular challenges such as reliability, performance, and power constraints. Monitoring became a necessary part for testing, debugging and performance evaluations of SoCs at run time, as On-chip monitoring is employed to provide environmental information, such as temperature, voltage, and error data. Real-time system validation is done by exploiting the monitoring to determine the proper operation of a system within the designed parameters. The paper explains the common monitoring operations in SoCs, showing the functionality of thermal, voltage and soft error monitors. The different architectures that are approached by the research community until now are discussed. IEEE Conference or Workshop Item NonPeerReviewed Rahimipour, S. and Rokhani, Fakhrul Zaman and Shafie, Suhaidi and El-Azhary, I. and Flayyih, W.N. A survey of on-chip monitors. In: 2012 International Conference on Circuits and Systems (ICCAS), 3-4 Oct. 2012, Kuala Lumpur. (pp. 243-248). 10.1109/ICCircuitsAndSystems.2012.6408286 |
| spellingShingle | Rahimipour, S. Rokhani, Fakhrul Zaman Shafie, Suhaidi El-Azhary, I. Flayyih, W.N. A survey of on-chip monitors |
| title | A survey of on-chip monitors |
| title_full | A survey of on-chip monitors |
| title_fullStr | A survey of on-chip monitors |
| title_full_unstemmed | A survey of on-chip monitors |
| title_short | A survey of on-chip monitors |
| title_sort | survey of on chip monitors |
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