Cell drop threshold architecture for multi-class shared buffer with finite memory size
Shared buffer is commonly used to utilize the buffer in the switch. In order to minimize the cell lost of high class traffic in multi-class switch, the threshold is set to drop the low class cells in the shared buffer. This will give more space to accommodate the high class traffic cells. In this pa...
| Main Authors: | , , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2011
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| Online Access: | http://psasir.upm.edu.my/id/eprint/45292/1/Cell%20drop%20threshold%20architecture%20for%20multi-class%20shared%20buffer%20with%20finite%20memory%20size.pdf |
| _version_ | 1825929560431001600 |
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| author | Abdul Rahman, Abdul Aziz Seman, Kamaruzzaman Saadan, Kamarudin Samingan, Ahmad Kamsani Azman, Azreen |
| author_facet | Abdul Rahman, Abdul Aziz Seman, Kamaruzzaman Saadan, Kamarudin Samingan, Ahmad Kamsani Azman, Azreen |
| author_sort | Abdul Rahman, Abdul Aziz |
| collection | UPM |
| description | Shared buffer is commonly used to utilize the buffer in the switch. In order to minimize the cell lost of high class traffic in multi-class switch, the threshold is set to drop the low class cells in the shared buffer. This will give more space to accommodate the high class traffic cells. In this paper, we analyse the performance of shared buffer with different threshold settings. The multi-class shared buffer architecture is developed for 16x16 ports switch, which is targeted for Xilinx FPGA implementation. The performance of the multi-class shared buffer switch is analysed in term of the achievable throughput as well as the drop probability. Based on the simulation with different threshold settings, it is observed that the optimum selection of cell drop threshold depends on the size of the shared buffer that triggers the RAM threshold. |
| first_indexed | 2024-03-06T08:58:31Z |
| format | Conference or Workshop Item |
| id | upm.eprints-45292 |
| institution | Universiti Putra Malaysia |
| language | English |
| last_indexed | 2024-03-06T08:58:31Z |
| publishDate | 2011 |
| publisher | IEEE |
| record_format | dspace |
| spelling | upm.eprints-452922020-08-05T06:48:25Z http://psasir.upm.edu.my/id/eprint/45292/ Cell drop threshold architecture for multi-class shared buffer with finite memory size Abdul Rahman, Abdul Aziz Seman, Kamaruzzaman Saadan, Kamarudin Samingan, Ahmad Kamsani Azman, Azreen Shared buffer is commonly used to utilize the buffer in the switch. In order to minimize the cell lost of high class traffic in multi-class switch, the threshold is set to drop the low class cells in the shared buffer. This will give more space to accommodate the high class traffic cells. In this paper, we analyse the performance of shared buffer with different threshold settings. The multi-class shared buffer architecture is developed for 16x16 ports switch, which is targeted for Xilinx FPGA implementation. The performance of the multi-class shared buffer switch is analysed in term of the achievable throughput as well as the drop probability. Based on the simulation with different threshold settings, it is observed that the optimum selection of cell drop threshold depends on the size of the shared buffer that triggers the RAM threshold. IEEE 2011 Conference or Workshop Item PeerReviewed text en http://psasir.upm.edu.my/id/eprint/45292/1/Cell%20drop%20threshold%20architecture%20for%20multi-class%20shared%20buffer%20with%20finite%20memory%20size.pdf Abdul Rahman, Abdul Aziz and Seman, Kamaruzzaman and Saadan, Kamarudin and Samingan, Ahmad Kamsani and Azman, Azreen (2011) Cell drop threshold architecture for multi-class shared buffer with finite memory size. In: 2011 IEEE Conference on Computer Applications and Industrial Electronics (ICCAIE 2011), 4-7 Dec. 2011, Penang, Malaysia. (pp. 319-324). 10.1109/ICCAIE.2011.6162153 |
| spellingShingle | Abdul Rahman, Abdul Aziz Seman, Kamaruzzaman Saadan, Kamarudin Samingan, Ahmad Kamsani Azman, Azreen Cell drop threshold architecture for multi-class shared buffer with finite memory size |
| title | Cell drop threshold architecture for multi-class shared buffer with finite memory size |
| title_full | Cell drop threshold architecture for multi-class shared buffer with finite memory size |
| title_fullStr | Cell drop threshold architecture for multi-class shared buffer with finite memory size |
| title_full_unstemmed | Cell drop threshold architecture for multi-class shared buffer with finite memory size |
| title_short | Cell drop threshold architecture for multi-class shared buffer with finite memory size |
| title_sort | cell drop threshold architecture for multi class shared buffer with finite memory size |
| url | http://psasir.upm.edu.my/id/eprint/45292/1/Cell%20drop%20threshold%20architecture%20for%20multi-class%20shared%20buffer%20with%20finite%20memory%20size.pdf |
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