3-level automotive safety warning and alert system using FPGA

This paper presents a safety warning system on automotive with 3 warning level according to conditions. The system is designed based on the Lane Departure Warning (LDW) system. This system is expected to reduce or minimize the road accident happened due to risky and careless driving. In the system,...

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Main Authors: Yeoh, Yoeng Jye, Jaafar, Haslina, Wan Hasan, Wan Zuha
Format: Conference or Workshop Item
Language:English
Published: IEEE 2015
Online Access:http://psasir.upm.edu.my/id/eprint/55640/1/3-level%20automotive%20safety%20warning%20and%20alert%20system%20using%20FPGA.pdf
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author Yeoh, Yoeng Jye
Jaafar, Haslina
Wan Hasan, Wan Zuha
author_facet Yeoh, Yoeng Jye
Jaafar, Haslina
Wan Hasan, Wan Zuha
author_sort Yeoh, Yoeng Jye
collection UPM
description This paper presents a safety warning system on automotive with 3 warning level according to conditions. The system is designed based on the Lane Departure Warning (LDW) system. This system is expected to reduce or minimize the road accident happened due to risky and careless driving. In the system, several sensors are embedded such as sonar wave sensors and camera. The system is designed using FPGA DE1 board as the design currently is in prototype stage. Several interface such as LCD, LED, and seven segment display are used. The maximum response time is about 3ms, and for longer range detection of sonar wave sensor, the longer the time required. Thus, the blind spot detection module and the camera module are independent, to improve the response time of the system, even though the warning alarm gives are dependent on each other.
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institution Universiti Putra Malaysia
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spelling upm.eprints-556402017-06-07T04:52:39Z http://psasir.upm.edu.my/id/eprint/55640/ 3-level automotive safety warning and alert system using FPGA Yeoh, Yoeng Jye Jaafar, Haslina Wan Hasan, Wan Zuha This paper presents a safety warning system on automotive with 3 warning level according to conditions. The system is designed based on the Lane Departure Warning (LDW) system. This system is expected to reduce or minimize the road accident happened due to risky and careless driving. In the system, several sensors are embedded such as sonar wave sensors and camera. The system is designed using FPGA DE1 board as the design currently is in prototype stage. Several interface such as LCD, LED, and seven segment display are used. The maximum response time is about 3ms, and for longer range detection of sonar wave sensor, the longer the time required. Thus, the blind spot detection module and the camera module are independent, to improve the response time of the system, even though the warning alarm gives are dependent on each other. IEEE 2015 Conference or Workshop Item PeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/55640/1/3-level%20automotive%20safety%20warning%20and%20alert%20system%20using%20FPGA.pdf Yeoh, Yoeng Jye and Jaafar, Haslina and Wan Hasan, Wan Zuha (2015) 3-level automotive safety warning and alert system using FPGA. In: 2015 IEEE International Circuits and Systems Symposium (ICSyS 2015), 2-4 Sept. 2015, Holiday Villa Beach Resort & Spa, Langkawi, Kedah. (pp. 125-129). 10.1109/CircuitsAndSystems.2015.7394078
spellingShingle Yeoh, Yoeng Jye
Jaafar, Haslina
Wan Hasan, Wan Zuha
3-level automotive safety warning and alert system using FPGA
title 3-level automotive safety warning and alert system using FPGA
title_full 3-level automotive safety warning and alert system using FPGA
title_fullStr 3-level automotive safety warning and alert system using FPGA
title_full_unstemmed 3-level automotive safety warning and alert system using FPGA
title_short 3-level automotive safety warning and alert system using FPGA
title_sort 3 level automotive safety warning and alert system using fpga
url http://psasir.upm.edu.my/id/eprint/55640/1/3-level%20automotive%20safety%20warning%20and%20alert%20system%20using%20FPGA.pdf
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AT jaafarhaslina 3levelautomotivesafetywarningandalertsystemusingfpga
AT wanhasanwanzuha 3levelautomotivesafetywarningandalertsystemusingfpga