Sub-picosecond jitter resolution wide range digital delay line for SoC integration
A novel three-stage architecture programmable digital delay line (DDL) with a picosecond resolution, 1μs range, and sub-picosecond jitter performance is proposed. Through circuit simulation, a dynamic range of 1μs is obtained in the first stage using 10-bit counters operating at a frequency of 1 GHz...
| Main Authors: | , , , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2015
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| Online Access: | http://psasir.upm.edu.my/id/eprint/55971/1/Sub-picosecond%20jitter%20resolution%20wide%20range%20digital%20delay%20line%20for%20SoC%20integration.pdf |
| _version_ | 1825931323757297664 |
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| author | Abdulrazzaq, Bilal Isam Abdul Halin, Izhal Mohd Sidek, Roslina Shafie, Suhaidi Md Yunus, Nurul Amziah Kawahito, Shoji |
| author_facet | Abdulrazzaq, Bilal Isam Abdul Halin, Izhal Mohd Sidek, Roslina Shafie, Suhaidi Md Yunus, Nurul Amziah Kawahito, Shoji |
| author_sort | Abdulrazzaq, Bilal Isam |
| collection | UPM |
| description | A novel three-stage architecture programmable digital delay line (DDL) with a picosecond resolution, 1μs range, and sub-picosecond jitter performance is proposed. Through circuit simulation, a dynamic range of 1μs is obtained in the first stage using 10-bit counters operating at a frequency of 1 GHz. The second stage further refines the delay to 23ps using a tapped inverter chain architecture. Finally, the third stage constructed using a DLL with NAND gate based delay elements further refines the delay step to 1ps resolution with a 0.1ps RMS jitter performance. The proposed digital delay line is designed using a standard 0.13μm Silterra CMOS technology. |
| first_indexed | 2024-03-06T09:25:00Z |
| format | Conference or Workshop Item |
| id | upm.eprints-55971 |
| institution | Universiti Putra Malaysia |
| language | English |
| last_indexed | 2024-03-06T09:25:00Z |
| publishDate | 2015 |
| publisher | IEEE |
| record_format | dspace |
| spelling | upm.eprints-559712017-07-03T09:25:53Z http://psasir.upm.edu.my/id/eprint/55971/ Sub-picosecond jitter resolution wide range digital delay line for SoC integration Abdulrazzaq, Bilal Isam Abdul Halin, Izhal Mohd Sidek, Roslina Shafie, Suhaidi Md Yunus, Nurul Amziah Kawahito, Shoji A novel three-stage architecture programmable digital delay line (DDL) with a picosecond resolution, 1μs range, and sub-picosecond jitter performance is proposed. Through circuit simulation, a dynamic range of 1μs is obtained in the first stage using 10-bit counters operating at a frequency of 1 GHz. The second stage further refines the delay to 23ps using a tapped inverter chain architecture. Finally, the third stage constructed using a DLL with NAND gate based delay elements further refines the delay step to 1ps resolution with a 0.1ps RMS jitter performance. The proposed digital delay line is designed using a standard 0.13μm Silterra CMOS technology. IEEE 2015 Conference or Workshop Item PeerReviewed application/pdf en http://psasir.upm.edu.my/id/eprint/55971/1/Sub-picosecond%20jitter%20resolution%20wide%20range%20digital%20delay%20line%20for%20SoC%20integration.pdf Abdulrazzaq, Bilal Isam and Abdul Halin, Izhal and Mohd Sidek, Roslina and Shafie, Suhaidi and Md Yunus, Nurul Amziah and Kawahito, Shoji (2015) Sub-picosecond jitter resolution wide range digital delay line for SoC integration. In: 2015 IEEE International Circuits and Systems Symposium (ICSyS 2015), 2-4 Sept. 2015, Holiday Villa Beach Resort & Spa, Langkawi, Kedah. (pp. 44-48). 10.1109/CircuitsAndSystems.2015.7394062 |
| spellingShingle | Abdulrazzaq, Bilal Isam Abdul Halin, Izhal Mohd Sidek, Roslina Shafie, Suhaidi Md Yunus, Nurul Amziah Kawahito, Shoji Sub-picosecond jitter resolution wide range digital delay line for SoC integration |
| title | Sub-picosecond jitter resolution wide range digital delay line for SoC integration |
| title_full | Sub-picosecond jitter resolution wide range digital delay line for SoC integration |
| title_fullStr | Sub-picosecond jitter resolution wide range digital delay line for SoC integration |
| title_full_unstemmed | Sub-picosecond jitter resolution wide range digital delay line for SoC integration |
| title_short | Sub-picosecond jitter resolution wide range digital delay line for SoC integration |
| title_sort | sub picosecond jitter resolution wide range digital delay line for soc integration |
| url | http://psasir.upm.edu.my/id/eprint/55971/1/Sub-picosecond%20jitter%20resolution%20wide%20range%20digital%20delay%20line%20for%20SoC%20integration.pdf |
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