Cooperative virtual channel router for adaptive hardwired FPGA network-on-chip
In this paper, the FPGA architecture having a hardwired network-on-chip (NoC) as system-level interconnect resource with adaptive router to support ranges of traffic condition. The proposed adaptive routers cooperatively allocate the virtual channel to minimizes the cost of supporting a wide range o...
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Format: | Conference or Workshop Item |
Language: | English |
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IEEE
2016
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Online Access: | http://psasir.upm.edu.my/id/eprint/59421/1/Cooperative%20virtual%20channel%20router%20for%20adaptive%20hardwired%20FPGA%20network-on-chip.pdf |
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author | Zakaria, Fazrul Faiz Abdul Latiff, Nurul Adilah Hashim, Shaiful Jahari Ehkan, Phaklen Rokhani, Fakhrul Zaman |
author_facet | Zakaria, Fazrul Faiz Abdul Latiff, Nurul Adilah Hashim, Shaiful Jahari Ehkan, Phaklen Rokhani, Fakhrul Zaman |
author_sort | Zakaria, Fazrul Faiz |
collection | UPM |
description | In this paper, the FPGA architecture having a hardwired network-on-chip (NoC) as system-level interconnect resource with adaptive router to support ranges of traffic condition. The proposed adaptive routers cooperatively allocate the virtual channel to minimizes the cost of supporting a wide range of traffic requirements from various FPGA application design instances. Simulation results show performance augmentation of 25% on average over an equal-size standard router, or achieve iso-performance using 50% less virtual channel buffer size. |
first_indexed | 2024-03-06T09:35:14Z |
format | Conference or Workshop Item |
id | upm.eprints-59421 |
institution | Universiti Putra Malaysia |
language | English |
last_indexed | 2024-03-06T09:35:14Z |
publishDate | 2016 |
publisher | IEEE |
record_format | dspace |
spelling | upm.eprints-594212018-03-02T03:30:32Z http://psasir.upm.edu.my/id/eprint/59421/ Cooperative virtual channel router for adaptive hardwired FPGA network-on-chip Zakaria, Fazrul Faiz Abdul Latiff, Nurul Adilah Hashim, Shaiful Jahari Ehkan, Phaklen Rokhani, Fakhrul Zaman In this paper, the FPGA architecture having a hardwired network-on-chip (NoC) as system-level interconnect resource with adaptive router to support ranges of traffic condition. The proposed adaptive routers cooperatively allocate the virtual channel to minimizes the cost of supporting a wide range of traffic requirements from various FPGA application design instances. Simulation results show performance augmentation of 25% on average over an equal-size standard router, or achieve iso-performance using 50% less virtual channel buffer size. IEEE 2016 Conference or Workshop Item PeerReviewed text en http://psasir.upm.edu.my/id/eprint/59421/1/Cooperative%20virtual%20channel%20router%20for%20adaptive%20hardwired%20FPGA%20network-on-chip.pdf Zakaria, Fazrul Faiz and Abdul Latiff, Nurul Adilah and Hashim, Shaiful Jahari and Ehkan, Phaklen and Rokhani, Fakhrul Zaman (2016) Cooperative virtual channel router for adaptive hardwired FPGA network-on-chip. In: 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 25-28 Oct. 2016, Jeju, South Korea. (pp. 358-361). 10.1109/APCCAS.2016.7803975 |
spellingShingle | Zakaria, Fazrul Faiz Abdul Latiff, Nurul Adilah Hashim, Shaiful Jahari Ehkan, Phaklen Rokhani, Fakhrul Zaman Cooperative virtual channel router for adaptive hardwired FPGA network-on-chip |
title | Cooperative virtual channel router for adaptive hardwired FPGA network-on-chip |
title_full | Cooperative virtual channel router for adaptive hardwired FPGA network-on-chip |
title_fullStr | Cooperative virtual channel router for adaptive hardwired FPGA network-on-chip |
title_full_unstemmed | Cooperative virtual channel router for adaptive hardwired FPGA network-on-chip |
title_short | Cooperative virtual channel router for adaptive hardwired FPGA network-on-chip |
title_sort | cooperative virtual channel router for adaptive hardwired fpga network on chip |
url | http://psasir.upm.edu.my/id/eprint/59421/1/Cooperative%20virtual%20channel%20router%20for%20adaptive%20hardwired%20FPGA%20network-on-chip.pdf |
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