New tool for converting high-level representations of finite state machines to verilog HDL
Automated conversion of high-level representation of Finite State Machine (FSM) to correct-by-construction Hardware Description Language (HDL) is of demand with the increasing complexity of the modern digital controller designs. In this paper, we proposed a tool implementing systematic methodology f...
| Main Authors: | , , |
|---|---|
| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2017
|
| Online Access: | http://psasir.upm.edu.my/id/eprint/59460/1/New%20tool%20for%20converting%20high-level%20representations%20of%20finite%20state%20machines%20to%20verilog%20HDL.pdf |
| _version_ | 1825932004703600640 |
|---|---|
| author | Masoumidezfouli, Seyedhossein Syed Mohamed, Syed Abdul Rahman Al-Haddad Rokhani, Fakhrul Zaman |
| author_facet | Masoumidezfouli, Seyedhossein Syed Mohamed, Syed Abdul Rahman Al-Haddad Rokhani, Fakhrul Zaman |
| author_sort | Masoumidezfouli, Seyedhossein |
| collection | UPM |
| description | Automated conversion of high-level representation of Finite State Machine (FSM) to correct-by-construction Hardware Description Language (HDL) is of demand with the increasing complexity of the modern digital controller designs. In this paper, we proposed a tool implementing systematic methodology for conversion and verification of high-level FSM to Verilog HDL. User defined options are provided to increase the flexibility and usability of the tool. MCNC91 benchmarks were used to evaluate the tool performance and correctness. Results indicate that the tool is able to correctly convert all given benchmark circuits with good runtime and memory consumption. |
| first_indexed | 2024-03-06T09:35:20Z |
| format | Conference or Workshop Item |
| id | upm.eprints-59460 |
| institution | Universiti Putra Malaysia |
| language | English |
| last_indexed | 2024-03-06T09:35:20Z |
| publishDate | 2017 |
| publisher | IEEE |
| record_format | dspace |
| spelling | upm.eprints-594602018-03-06T02:33:53Z http://psasir.upm.edu.my/id/eprint/59460/ New tool for converting high-level representations of finite state machines to verilog HDL Masoumidezfouli, Seyedhossein Syed Mohamed, Syed Abdul Rahman Al-Haddad Rokhani, Fakhrul Zaman Automated conversion of high-level representation of Finite State Machine (FSM) to correct-by-construction Hardware Description Language (HDL) is of demand with the increasing complexity of the modern digital controller designs. In this paper, we proposed a tool implementing systematic methodology for conversion and verification of high-level FSM to Verilog HDL. User defined options are provided to increase the flexibility and usability of the tool. MCNC91 benchmarks were used to evaluate the tool performance and correctness. Results indicate that the tool is able to correctly convert all given benchmark circuits with good runtime and memory consumption. IEEE 2017 Conference or Workshop Item PeerReviewed text en http://psasir.upm.edu.my/id/eprint/59460/1/New%20tool%20for%20converting%20high-level%20representations%20of%20finite%20state%20machines%20to%20verilog%20HDL.pdf Masoumidezfouli, Seyedhossein and Syed Mohamed, Syed Abdul Rahman Al-Haddad and Rokhani, Fakhrul Zaman (2017) New tool for converting high-level representations of finite state machines to verilog HDL. In: 2017 IEEE 15th Student Conference on Research and Development (SCOReD), 13-14 Dec. 2017, Putrajaya, Malaysia. (pp. 1-6). 10.1109/SCORED.2017.8305431 |
| spellingShingle | Masoumidezfouli, Seyedhossein Syed Mohamed, Syed Abdul Rahman Al-Haddad Rokhani, Fakhrul Zaman New tool for converting high-level representations of finite state machines to verilog HDL |
| title | New tool for converting high-level representations of finite state machines to verilog HDL |
| title_full | New tool for converting high-level representations of finite state machines to verilog HDL |
| title_fullStr | New tool for converting high-level representations of finite state machines to verilog HDL |
| title_full_unstemmed | New tool for converting high-level representations of finite state machines to verilog HDL |
| title_short | New tool for converting high-level representations of finite state machines to verilog HDL |
| title_sort | new tool for converting high level representations of finite state machines to verilog hdl |
| url | http://psasir.upm.edu.my/id/eprint/59460/1/New%20tool%20for%20converting%20high-level%20representations%20of%20finite%20state%20machines%20to%20verilog%20HDL.pdf |
| work_keys_str_mv | AT masoumidezfouliseyedhossein newtoolforconvertinghighlevelrepresentationsoffinitestatemachinestoveriloghdl AT syedmohamedsyedabdulrahmanalhaddad newtoolforconvertinghighlevelrepresentationsoffinitestatemachinestoveriloghdl AT rokhanifakhrulzaman newtoolforconvertinghighlevelrepresentationsoffinitestatemachinestoveriloghdl |