FPGA implementation of the proposed DSI-SLM scheme for PAPR reduction in OFDM systems
High peak to average power ratio (PAPR) is the main drawback of orthogonal frequency division multiplexing (OFDM) systems. Some of the proposed PAPR reduction solutions are dummy insertion (DSI), selected mapping (SLM) and combined DSI-SLM scheme. This paper presents FPGA implementation of DSI-SLM s...
| Egile Nagusiak: | , , , , |
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| Formatua: | Conference or Workshop Item |
| Hizkuntza: | English |
| Argitaratua: |
IEEE
2011
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| Sarrera elektronikoa: | http://psasir.upm.edu.my/id/eprint/68248/1/FPGA%20implementation%20of%20the%20proposed%20DSI-SLM%20scheme%20for%20PAPR%20reduction%20in%20OFDM%20systems.pdf |
| Gaia: | High peak to average power ratio (PAPR) is the main drawback of orthogonal frequency division multiplexing (OFDM) systems. Some of the proposed PAPR reduction solutions are dummy insertion (DSI), selected mapping (SLM) and combined DSI-SLM scheme. This paper presents FPGA implementation of DSI-SLM scheme for OFDM signals. The results of the implementation and simulation are compared which show that the PAPR is almost the same as simulation results. The hardware resource consumption of the DSI-SLM method is estimated to be at least 4 times less than conventional SLM (C-SLM) method with comparable PAPR performance. |
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