Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus
In this paper, the technique of optimal interconnects width and spacing is analyzed to reduce the area, delay and area-delay-product of multi-level signaling on-chip bus. To capture the delay impact from cross-coupling capacitance in the deep sub-micron on-chip bus, the Miller Capacitance Factor (MC...
| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2010
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| Online Access: | http://psasir.upm.edu.my/id/eprint/68598/1/Interconnect%20area%2C%20delay%20and%20area-delay%20optimization%20for%20multi-level%20signaling%20on-chip%20bus.pdf |
| _version_ | 1825933558365028352 |
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| author | Mai, Yoong Ching Ang, Tun Boon Chin, Kock Yeong Rokhani, Fakhrul Zaman |
| author_facet | Mai, Yoong Ching Ang, Tun Boon Chin, Kock Yeong Rokhani, Fakhrul Zaman |
| author_sort | Mai, Yoong Ching |
| collection | UPM |
| description | In this paper, the technique of optimal interconnects width and spacing is analyzed to reduce the area, delay and area-delay-product of multi-level signaling on-chip bus. To capture the delay impact from cross-coupling capacitance in the deep sub-micron on-chip bus, the Miller Capacitance Factor (MCF) for 4-level signals is developed. Results show that our proposed technique reveals the trade-off between bus area and delay to achieve the optimized bus configuration. |
| first_indexed | 2024-03-06T09:59:07Z |
| format | Conference or Workshop Item |
| id | upm.eprints-68598 |
| institution | Universiti Putra Malaysia |
| language | English |
| last_indexed | 2024-03-06T09:59:07Z |
| publishDate | 2010 |
| publisher | IEEE |
| record_format | dspace |
| spelling | upm.eprints-685982020-07-06T07:14:14Z http://psasir.upm.edu.my/id/eprint/68598/ Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus Mai, Yoong Ching Ang, Tun Boon Chin, Kock Yeong Rokhani, Fakhrul Zaman In this paper, the technique of optimal interconnects width and spacing is analyzed to reduce the area, delay and area-delay-product of multi-level signaling on-chip bus. To capture the delay impact from cross-coupling capacitance in the deep sub-micron on-chip bus, the Miller Capacitance Factor (MCF) for 4-level signals is developed. Results show that our proposed technique reveals the trade-off between bus area and delay to achieve the optimized bus configuration. IEEE 2010 Conference or Workshop Item PeerReviewed text en http://psasir.upm.edu.my/id/eprint/68598/1/Interconnect%20area%2C%20delay%20and%20area-delay%20optimization%20for%20multi-level%20signaling%20on-chip%20bus.pdf Mai, Yoong Ching and Ang, Tun Boon and Chin, Kock Yeong and Rokhani, Fakhrul Zaman (2010) Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus. In: 2010 Asia Pacific Conference on Circuit and System (APCCAS 2010), 6-9 Dec. 2010, Kuala Lumpur, Malaysia. (pp. 1143-1146). 10.1109/APCCAS.2010.5775086 |
| spellingShingle | Mai, Yoong Ching Ang, Tun Boon Chin, Kock Yeong Rokhani, Fakhrul Zaman Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus |
| title | Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus |
| title_full | Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus |
| title_fullStr | Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus |
| title_full_unstemmed | Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus |
| title_short | Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus |
| title_sort | interconnect area delay and area delay optimization for multi level signaling on chip bus |
| url | http://psasir.upm.edu.my/id/eprint/68598/1/Interconnect%20area%2C%20delay%20and%20area-delay%20optimization%20for%20multi-level%20signaling%20on-chip%20bus.pdf |
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