Investigating the impact of on-chip interconnection noise on dynamic thermal management efficiency

Investigating the impact of on-chip interconnection noise on dynamic thermal management efficiency

Show other versions (1)

Dynamic Thermal Management (DTM) emerged as a solution to address the reliability challenges with thermal hotspots and unbalanced temperatures. DTM efficiency is highly affected by the accuracy of the temperature information presented to the DTM manager. This work aims to investigate the effect of i...

Full description

Bibliographic Details
Main Authors:	Rahimipour, Somayeh, Flayyih, Wameedh Nazar, Kamsani, Noor Ain, Stan, Mircea, Rokhani, Fakhrul Zaman
Format:	Conference or Workshop Item
Language:	English
Published:	IEEE 2015
Online Access:	http://psasir.upm.edu.my/id/eprint/69673/1/Investigating%20the%20impact%20of%20on-chip%20interconnection%20noise%20on%20dynamic%20thermal%20management%20efficiency.pdf

Similar Items

Investigating the impact of on-chip interconnection noise on dynamic thermal management efficiency
by: Rahimipour, Somayeh, et al.
Published: (2015)

Low-power, highly reliable dynamic thermal management by exploiting approximate computing
by: Rahimipour, Somayeh, et al.
Published: (2020)

Reliability analysis of multibit error correcting coding and comparison to hamming product code for on-chip interconnect
by: Chlaab, Asaad Kadhum, et al.
Published: (2020)

Reliability Analysis of Multibit Error Correcting Coding and Comparison to Hamming Product Code for On-Chip Interconnect
by: Asaad chlab kadum, et al.
Published: (2020-06-01)

Lightweight hamming product code based multiple bit error correction coding scheme using shared resources for on chip interconnects
by: Chlaab, Asaad Kadhum, et al.
Published: (2020)

Tolerating permanent faults in the input port of the network on chip router
by: Mohammed, Hala J., et al.
Published: (2019)

A survey of on-chip monitors
by: Rahimipour, S., et al.

Adaptive multibit crosstalk-aware error control coding scheme for on-chip communication
by: Flayyih, Wameedh Nazar, et al.
Published: (2016)

Crosstalk-aware error control coding techniques for reliable and energy efficient network on chip
by: Flayyih, Wameedh Nazar
Published: (2014)

Multi-bit error control coding with limited correction for high-performance and energy- efficient network on chip
by: Flayyih, Wameedh N., et al.
Published: (2019)

Tolerating Permanent Faults in the Input Port of the Network on Chip Router
by: Hala J. Mohammed, et al.
Published: (2019-02-01)

Crosstalk-aware multiple error detection scheme based on two-dimensional parities for energy efficient network on chip
by: Flayyih, Wameedh N., et al.
Published: (2014)

Area efficient test circuit for library standard cell qualification
by: Al-Frajat, Jaafar Khadair Kadam, et al.
Published: (2015)

Comparative Reliability Analysis between Horizontal-Vertical-Diagonal Code and Code with Crosstalk Avoidance and Error Correction for NoC Interconnects
by: Hamdan Kadhim Abed, et al.
Published: (2023-07-01)

Improved undetected error probability model for JTEC and JTEC-SQED coding schemes
by: Flayyih, Wameedh Nazar, et al.
Published: (2013)

Interconnect area, delay and area-delay optimization for multi-level signaling on-chip bus
by: Mai, Yoong Ching, et al.
Published: (2010)

Development of automated standard cell library characterization (ASCLIC) for nanometer system-on-chip design
by: Hussin, Muhammad Syafiq Izzat, et al.
Published: (2017)

Energy efficient 8-bit microprocessor for wireless sensor network applications
by: Hoon, Yap, et al.
Published: (2013)

ADDING PERFECT FORWARD SECRECY TO KERBEROS
by: Wameedh Nazar Flayyih
Published: (2010-04-01)

Reduced hardware architecture for energy-efficient IoT healthcare sensor nodes
by: Lim, Yang Wei, et al.
Published: (2015)

Addressing fault tolerance in 4-PAM signaling by using block codes for on/off-chip communication
by: Forooshani, Arash Abtahi, et al.
Published: (2011)

Hardware software partitioning of crankshaft function in engine control units using FPGA-based testing
by: Yeoh, Khai Chein, et al.
Published: (2017)

Evaluation of optimum scan chain parameter with respect to its power performance of CORTEXM0DS
by: Latip, Nur Amirah, et al.
Published: (2017)

Analysis and modeling of ASIC area at early-stage design for standard cell library selection
by: Lim, Yang Wei, et al.
Published: (2019)

A 1 V -21 dBm threshold voltage compensated rectifier for radio frequency energy harvesting
by: Zareianjahromi, Seyed Arash, et al.
Published: (2022)

Energy-Performance Optimization via P/N Ratio Sizing With Full Diffusion Layout Structure and Standard Cell Height Tuning in Near-Threshold Voltage Operation
by: Yang Wei Lim, et al.
Published: (2023-01-01)

Energy-performance optimization via P/N ratio sizing with full diffusion layout structure and standard cell height tuning in near-threshold voltage operation
by: Lim, Yang Wei, et al.
Published: (2022)

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor
by: Shokrani, Mohammad Reza, et al.
Published: (2014)

Power - reliability tradeoff in low power 4-PAM signaling in on-chip communication
by: Forooshani, Arash Abtahi, et al.
Published: (2011)

On-chip communication architectures : system on chip interconnect /
by: 367191 Pasricha, Sudeep, et al.
Published: (2008)

The Other Face of On-Chip Interconnect
by: Agarwal, Anant
Published: (2010)

Dynamic noise analysis for 4-PAM signaling scheme
by: Forooshani, Arash Abtahi, et al.

Point-to-point protocol implementation using atmel micro controller [microfilm] /
by: Fakhrul Zaman Rokhani
Published: (2001)

GRATING-ASSISTED WAVE-GUIDE CHIP-TO-CHIP INTERCONNECTS
by: Chan, G, et al.
Published: (1994)

A process variation aware system-level framework to model on-chip communication system in support of fault tolerant analysis
by: Forooshani, Arash Abtahi, et al.
Published: (2009)

Designing Energy-Efficient Low-Diameter On-chip Networks with Equalized Interconnects
by: Joshi, Ajay J., et al.
Published: (2010)

Cooperative virtual channel router for adaptive hardwired FPGA network-on-chip
by: Zakaria, Fazrul Faiz, et al.
Published: (2016)

Generating power-optimal standard cell library specification using neural network technique
by: Lim, Sze Huang, et al.
Published: (2017)

Energy scalability of on-chip interconnection networks
by: Konstantakopoulos, Theodoros K., 1977-
Published: (2008)

Carbon nanotube interconnects for IC chips
by: Anwar Ali, Hashina Parveen
Published: (2007)