Embedded Parallel Systolic Architecture For Multi-Filtering Techniques Using FPGA.
Computing systems typically suffer from delay in data processing.
| Main Authors: | , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2010
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| Subjects: | |
| Online Access: | http://eprints.usm.my/21979/1/T380.pdf |