Tile-Level Parallelism For H.264/Avc Codec Using Parallel Domain Decomposition Algorithm On Shared Memory Architecture
Tema tesis ini adalah berdasarkan kepada penggunaan ciri-ciri model selari dalam fasa reka bentuk algoritma untuk mengurangkan kerumitan pengiraan dalam perbandingan dengan algoritma bersiri. Dengan menganggap bahawa seni bina selari membentuk majoriti pengiraan nod dalam peranti digital, cadanga...
| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2015
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| Subjects: | |
| Online Access: | http://eprints.usm.my/32297/1/MOHAMMED_F_EESSA.pdf |
| _version_ | 1825832686660354048 |
|---|---|
| author | Eessa, Mohammed F. |
| author_facet | Eessa, Mohammed F. |
| author_sort | Eessa, Mohammed F. |
| collection | USM |
| description | Tema tesis ini adalah berdasarkan kepada penggunaan ciri-ciri model selari
dalam fasa reka bentuk algoritma untuk mengurangkan kerumitan pengiraan dalam
perbandingan dengan algoritma bersiri. Dengan menganggap bahawa seni bina selari
membentuk majoriti pengiraan nod dalam peranti digital, cadangan bagi algoritma
selari-inheren adalah sesuai. Dalam karya ini, proses atau pengenalan bebenang
didaftar dalam satu formula matematik untuk mengurai domain satu, dua, dan
domain tiga dimensi. Penyelesaian senario ruang dua dimensi seterusnya disesuaikan
sebagai tahap baru keselarian untuk pengekodan piawaian H.264/AVC kerana
kerumitan pengiraan yang lebih tinggi daripada pengekodan video ini berbanding
dengan piawaian sebelumnya. Tahap baru keselarian untuk pengekod H.264 / AVC
ini telah direka untuk mempertimbangkan beberapa metrik pengekodean video dan
berorientasikan selari. Kaedah selari peringkat-jubin H.264/AVC yang dicadangkan
dibandingkan dengan pendekatan selari tahap kepingan dan tahap blok makro.
The theme of this thesis is based on the utilisation of features of the parallel
model in the design phase of an algorithm in order to reduce the computational
complexity in comparison with the serial algorithm. By assuming that parallel
architectures are forming the vast majority of computing nodes in digital devises,
proposing inherently-parallel algorithms are no more an overstatement. In this work,
the process or thread identification is used in a mathematical formulation to
decompose a one-, two, and a three-dimensional domain. Then, the solution of the
scenario of two-dimensional space is further customized to serve as a new level of
parallelism for the H.264/AVC coding standard due to the higher computational
complexity of this video coding in comparison with previous standards. This new
level of parallelism for the H.264/AVC encoder has been designed in a way to
consider several video coding and parallel- oriented metrics. As a further step, the
proposed tile-level parallel H.264/AVC is compared with the slice-level and the
macroblock-level parallel approaches. |
| first_indexed | 2024-03-06T14:56:33Z |
| format | Thesis |
| id | usm.eprints-32297 |
| institution | Universiti Sains Malaysia |
| language | English |
| last_indexed | 2024-03-06T14:56:33Z |
| publishDate | 2015 |
| record_format | dspace |
| spelling | usm.eprints-322972019-04-12T05:25:35Z http://eprints.usm.my/32297/ Tile-Level Parallelism For H.264/Avc Codec Using Parallel Domain Decomposition Algorithm On Shared Memory Architecture Eessa, Mohammed F. QA75.5-76.95 Electronic computers. Computer science Tema tesis ini adalah berdasarkan kepada penggunaan ciri-ciri model selari dalam fasa reka bentuk algoritma untuk mengurangkan kerumitan pengiraan dalam perbandingan dengan algoritma bersiri. Dengan menganggap bahawa seni bina selari membentuk majoriti pengiraan nod dalam peranti digital, cadangan bagi algoritma selari-inheren adalah sesuai. Dalam karya ini, proses atau pengenalan bebenang didaftar dalam satu formula matematik untuk mengurai domain satu, dua, dan domain tiga dimensi. Penyelesaian senario ruang dua dimensi seterusnya disesuaikan sebagai tahap baru keselarian untuk pengekodan piawaian H.264/AVC kerana kerumitan pengiraan yang lebih tinggi daripada pengekodan video ini berbanding dengan piawaian sebelumnya. Tahap baru keselarian untuk pengekod H.264 / AVC ini telah direka untuk mempertimbangkan beberapa metrik pengekodean video dan berorientasikan selari. Kaedah selari peringkat-jubin H.264/AVC yang dicadangkan dibandingkan dengan pendekatan selari tahap kepingan dan tahap blok makro. The theme of this thesis is based on the utilisation of features of the parallel model in the design phase of an algorithm in order to reduce the computational complexity in comparison with the serial algorithm. By assuming that parallel architectures are forming the vast majority of computing nodes in digital devises, proposing inherently-parallel algorithms are no more an overstatement. In this work, the process or thread identification is used in a mathematical formulation to decompose a one-, two, and a three-dimensional domain. Then, the solution of the scenario of two-dimensional space is further customized to serve as a new level of parallelism for the H.264/AVC coding standard due to the higher computational complexity of this video coding in comparison with previous standards. This new level of parallelism for the H.264/AVC encoder has been designed in a way to consider several video coding and parallel- oriented metrics. As a further step, the proposed tile-level parallel H.264/AVC is compared with the slice-level and the macroblock-level parallel approaches. 2015-10 Thesis NonPeerReviewed application/pdf en http://eprints.usm.my/32297/1/MOHAMMED_F_EESSA.pdf Eessa, Mohammed F. (2015) Tile-Level Parallelism For H.264/Avc Codec Using Parallel Domain Decomposition Algorithm On Shared Memory Architecture. PhD thesis, Universiti Sains Malaysia. |
| spellingShingle | QA75.5-76.95 Electronic computers. Computer science Eessa, Mohammed F. Tile-Level Parallelism For H.264/Avc Codec Using Parallel Domain Decomposition Algorithm On Shared Memory Architecture |
| title | Tile-Level Parallelism For H.264/Avc Codec Using Parallel Domain Decomposition Algorithm On Shared Memory Architecture |
| title_full | Tile-Level Parallelism For H.264/Avc Codec Using Parallel Domain Decomposition Algorithm On Shared Memory Architecture |
| title_fullStr | Tile-Level Parallelism For H.264/Avc Codec Using Parallel Domain Decomposition Algorithm On Shared Memory Architecture |
| title_full_unstemmed | Tile-Level Parallelism For H.264/Avc Codec Using Parallel Domain Decomposition Algorithm On Shared Memory Architecture |
| title_short | Tile-Level Parallelism For H.264/Avc Codec Using Parallel Domain Decomposition Algorithm On Shared Memory Architecture |
| title_sort | tile level parallelism for h 264 avc codec using parallel domain decomposition algorithm on shared memory architecture |
| topic | QA75.5-76.95 Electronic computers. Computer science |
| url | http://eprints.usm.my/32297/1/MOHAMMED_F_EESSA.pdf |
| work_keys_str_mv | AT eessamohammedf tilelevelparallelismforh264avccodecusingparalleldomaindecompositionalgorithmonsharedmemoryarchitecture |