Design And Simulation Of Cmos-Based Bandgap Reference Voltage With Compensation Circuit Using 0.18 Μm Process Technology
Voltage reference circuit is important in electronic world nowadays. A CMOS based bandgap reference (BGR) circuit is preferred due to its size is smaller and consume less power. However, the drawback is the reference voltage variation of CMOS based BGR circuit is big in wide range of temperature, th...
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| Format: | Thesis |
| Language: | English |
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2017
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| Online Access: | http://eprints.usm.my/37342/1/CHAN_MUN_KIT_24_Pages.pdf |
| _version_ | 1797009812068761600 |
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| author | Chan, Mun kit |
| author_facet | Chan, Mun kit |
| author_sort | Chan, Mun kit |
| collection | USM |
| description | Voltage reference circuit is important in electronic world nowadays. A CMOS based bandgap reference (BGR) circuit is preferred due to its size is smaller and consume less power. However, the drawback is the reference voltage variation of CMOS based BGR circuit is big in wide range of temperature, thus the temperature coefficient of it is high. Hence, an improved version of piecewise curvature-corrected Bandgap voltage reference circuit which has low voltage variation in wide range of temperature is introduced in this project to overcome the problem mentioned above. The BGR circuit is designed using CMOS compatible process in 0.18μm CMOS process technology and simulated by using Cadence tool. The proposed piecewise curvature-corrected BGR operate properly with output voltage of 558.6 mV to 558.3 mV by varying the voltage supply 1.4 V to 3.3 V at 27°C and the line regulation is 0.016% . Besides that, the best temperature coefficient obtained is 9.2 ppm/°C in the temperature range of -25°C to 150°C at 1.8 V. The PSSR of the proposed circuit is -69.91 dB at frequency less 10 kHz. The layout design of the proposed circuit is done by using Silterra 0.18 μm standard CMOS process and total die area is 0.0175 mm2 and temperature coefficient obtained in post layout simulation is 11.66ppm/°C. In short, it is found that the proposed design of BGR circuit is able to achieve high temperature range and relatively low voltage variation. |
| first_indexed | 2024-03-06T15:10:52Z |
| format | Thesis |
| id | usm.eprints-37342 |
| institution | Universiti Sains Malaysia |
| language | English |
| last_indexed | 2024-03-06T15:10:52Z |
| publishDate | 2017 |
| record_format | dspace |
| spelling | usm.eprints-373422019-04-12T05:25:06Z http://eprints.usm.my/37342/ Design And Simulation Of Cmos-Based Bandgap Reference Voltage With Compensation Circuit Using 0.18 Μm Process Technology Chan, Mun kit TK1-9971 Electrical engineering. Electronics. Nuclear engineering Voltage reference circuit is important in electronic world nowadays. A CMOS based bandgap reference (BGR) circuit is preferred due to its size is smaller and consume less power. However, the drawback is the reference voltage variation of CMOS based BGR circuit is big in wide range of temperature, thus the temperature coefficient of it is high. Hence, an improved version of piecewise curvature-corrected Bandgap voltage reference circuit which has low voltage variation in wide range of temperature is introduced in this project to overcome the problem mentioned above. The BGR circuit is designed using CMOS compatible process in 0.18μm CMOS process technology and simulated by using Cadence tool. The proposed piecewise curvature-corrected BGR operate properly with output voltage of 558.6 mV to 558.3 mV by varying the voltage supply 1.4 V to 3.3 V at 27°C and the line regulation is 0.016% . Besides that, the best temperature coefficient obtained is 9.2 ppm/°C in the temperature range of -25°C to 150°C at 1.8 V. The PSSR of the proposed circuit is -69.91 dB at frequency less 10 kHz. The layout design of the proposed circuit is done by using Silterra 0.18 μm standard CMOS process and total die area is 0.0175 mm2 and temperature coefficient obtained in post layout simulation is 11.66ppm/°C. In short, it is found that the proposed design of BGR circuit is able to achieve high temperature range and relatively low voltage variation. 2017 Thesis NonPeerReviewed application/pdf en http://eprints.usm.my/37342/1/CHAN_MUN_KIT_24_Pages.pdf Chan, Mun kit (2017) Design And Simulation Of Cmos-Based Bandgap Reference Voltage With Compensation Circuit Using 0.18 Μm Process Technology. Masters thesis, Universiti Sains Malaysia. |
| spellingShingle | TK1-9971 Electrical engineering. Electronics. Nuclear engineering Chan, Mun kit Design And Simulation Of Cmos-Based Bandgap Reference Voltage With Compensation Circuit Using 0.18 Μm Process Technology |
| title | Design And Simulation Of Cmos-Based Bandgap Reference Voltage With Compensation Circuit Using 0.18 Μm Process Technology |
| title_full | Design And Simulation Of Cmos-Based Bandgap Reference Voltage With Compensation Circuit Using 0.18 Μm Process Technology |
| title_fullStr | Design And Simulation Of Cmos-Based Bandgap Reference Voltage With Compensation Circuit Using 0.18 Μm Process Technology |
| title_full_unstemmed | Design And Simulation Of Cmos-Based Bandgap Reference Voltage With Compensation Circuit Using 0.18 Μm Process Technology |
| title_short | Design And Simulation Of Cmos-Based Bandgap Reference Voltage With Compensation Circuit Using 0.18 Μm Process Technology |
| title_sort | design and simulation of cmos based bandgap reference voltage with compensation circuit using 0 18 μm process technology |
| topic | TK1-9971 Electrical engineering. Electronics. Nuclear engineering |
| url | http://eprints.usm.my/37342/1/CHAN_MUN_KIT_24_Pages.pdf |
| work_keys_str_mv | AT chanmunkit designandsimulationofcmosbasedbandgapreferencevoltagewithcompensationcircuitusing018mmprocesstechnology |