| Summary: | Typically, only pass/fail basis test algorithm is being used to test the cache array in silicon devices. But the pass/fail basis test algorithm is insufficient to identify the failing characteristic of the cache array when it comes to the failure analysis (FA) and debug stage to find out the root cause of the failing mechanism. The resolution of test algorithm plays an important role in helping FA process to identify every single failing bits in cache array. In this dissertation, the concept of bringing up the Memory Build in Self-Test (MBIST) high resolution test pattern is discussed. The utilization of MBIST engine by insertion of the Capture Test Vector (CTV) element into the test algorithm is the main concept in increasing the resolution test pattern. At the same time, the importance of high resolution test pattern in FA process is being shown in a real case study. The generated high resolution test pattern is integrated for Automated Test Equipment (ATE) usage so that the test pattern can be applied in real silicon device testing. Then, a silicon device is edited using Focused Ion Beam (FIB) to destroy the memory bits in cache array for proving the test pattern is functioning properly. Finally, the high resolution test pattern is being used in real case application for proving the high resolution test pattern have the capability in improving FA efficiency in identifying the failing bits. The FA technique and application of using high resolution test pattern in debugging the cache failure are shown from the testing stage until the destructive FA stage. The finding in real case FA proved the concept of bring up the MBIST high resolution test pattern is working properly. It is able to increase the effectiveness of failure analysis and failure isolation process which indirectly increase the success rate for finding the root cause.
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