Pcie Ip Validation Process Across Process Corner, Voltage And Temperature Conditions
IP validation has become more challenging for FPGA device as it supports high operating speed. The Peripheral Component Interconnect Express (PCIe) is an IP used for high speed data transfer that supported by Intel FPGAs. The base specifications of PCIe 3.0 supports 8.0 GT/s, 5.0 GT/s and 2.5 GT/s....
| Main Author: | |
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| Format: | Thesis |
| Language: | English |
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2017
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| Online Access: | http://eprints.usm.my/39579/1/NURUL_IZYAN_BINTI_ABDUL_KARIM_24_Pages.pdf |
| _version_ | 1797010266164035584 |
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| author | Abdul Karim, Nurul Izyan |
| author_facet | Abdul Karim, Nurul Izyan |
| author_sort | Abdul Karim, Nurul Izyan |
| collection | USM |
| description | IP validation has become more challenging for FPGA device as it supports high operating speed. The Peripheral Component Interconnect Express (PCIe) is an IP used for high speed data transfer that supported by Intel FPGAs. The base specifications of PCIe 3.0 supports 8.0 GT/s, 5.0 GT/s and 2.5 GT/s. The link training and Initialization takes place at physical layer to initialize the link width and link data rate. The physical layer is getting more complex when it supports higher speed. The operational state only happens when Link Training and Status State Machine (LTSSM) reaches L0 state after device being configured. The stability of link training is improved by optimizing the soft logic design in application layer. Two protocol tests usually validated in industry are link up testing and link & higher layer testing. Debugging tools supported by Quartus are fully utilized to detect any failure during link training. The characterization of link performance covers process corners, voltage and temperature conditions are hard to analyze. By using hypothesis testing method, data collected gives a clear trend on the PCIe link performance. The H0 statement shows a significant difference for passing and failing case. In this research, the worst case happened at low voltage and low temperature regardless of any process corners. The p-value is greater than 0.05 proved H0 statement is accepted. The difference on passing and failing percentage is insignificantly impacting overall link performance of PCIe. It concludes that the bug is random and not caused by any defects on the silicon layout of FPGA device. Thus, IP validation shows the robustness of the device and able to comply with base specification of PCIe. |
| first_indexed | 2024-03-06T15:17:20Z |
| format | Thesis |
| id | usm.eprints-39579 |
| institution | Universiti Sains Malaysia |
| language | English |
| last_indexed | 2024-03-06T15:17:20Z |
| publishDate | 2017 |
| record_format | dspace |
| spelling | usm.eprints-395792019-04-12T05:25:05Z http://eprints.usm.my/39579/ Pcie Ip Validation Process Across Process Corner, Voltage And Temperature Conditions Abdul Karim, Nurul Izyan TK1-9971 Electrical engineering. Electronics. Nuclear engineering IP validation has become more challenging for FPGA device as it supports high operating speed. The Peripheral Component Interconnect Express (PCIe) is an IP used for high speed data transfer that supported by Intel FPGAs. The base specifications of PCIe 3.0 supports 8.0 GT/s, 5.0 GT/s and 2.5 GT/s. The link training and Initialization takes place at physical layer to initialize the link width and link data rate. The physical layer is getting more complex when it supports higher speed. The operational state only happens when Link Training and Status State Machine (LTSSM) reaches L0 state after device being configured. The stability of link training is improved by optimizing the soft logic design in application layer. Two protocol tests usually validated in industry are link up testing and link & higher layer testing. Debugging tools supported by Quartus are fully utilized to detect any failure during link training. The characterization of link performance covers process corners, voltage and temperature conditions are hard to analyze. By using hypothesis testing method, data collected gives a clear trend on the PCIe link performance. The H0 statement shows a significant difference for passing and failing case. In this research, the worst case happened at low voltage and low temperature regardless of any process corners. The p-value is greater than 0.05 proved H0 statement is accepted. The difference on passing and failing percentage is insignificantly impacting overall link performance of PCIe. It concludes that the bug is random and not caused by any defects on the silicon layout of FPGA device. Thus, IP validation shows the robustness of the device and able to comply with base specification of PCIe. 2017 Thesis NonPeerReviewed application/pdf en http://eprints.usm.my/39579/1/NURUL_IZYAN_BINTI_ABDUL_KARIM_24_Pages.pdf Abdul Karim, Nurul Izyan (2017) Pcie Ip Validation Process Across Process Corner, Voltage And Temperature Conditions. Masters thesis, Universiti Sains Malaysia. |
| spellingShingle | TK1-9971 Electrical engineering. Electronics. Nuclear engineering Abdul Karim, Nurul Izyan Pcie Ip Validation Process Across Process Corner, Voltage And Temperature Conditions |
| title | Pcie Ip Validation Process Across Process Corner, Voltage And Temperature Conditions |
| title_full | Pcie Ip Validation Process Across Process Corner, Voltage And Temperature Conditions |
| title_fullStr | Pcie Ip Validation Process Across Process Corner, Voltage And Temperature Conditions |
| title_full_unstemmed | Pcie Ip Validation Process Across Process Corner, Voltage And Temperature Conditions |
| title_short | Pcie Ip Validation Process Across Process Corner, Voltage And Temperature Conditions |
| title_sort | pcie ip validation process across process corner voltage and temperature conditions |
| topic | TK1-9971 Electrical engineering. Electronics. Nuclear engineering |
| url | http://eprints.usm.my/39579/1/NURUL_IZYAN_BINTI_ABDUL_KARIM_24_Pages.pdf |
| work_keys_str_mv | AT abdulkarimnurulizyan pcieipvalidationprocessacrossprocesscornervoltageandtemperatureconditions |