Rtl Implementation Of Secure Hash Algorithm 3 (Sha-3) Towards Smaller Area
Secure data transfer has been the most challenging task for Internet of Things (IoT) devices. Data integrity must be ensured before and after the data transmission. Cryptographic hash functions are generally the basis of a secure network and used for data integrity verification. Cryptographic hash f...
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| Format: | Thesis |
| Language: | English |
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2017
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| Online Access: | http://eprints.usm.my/39583/1/LIM_YEN_RUEN_24_Pages.pdf |
| _version_ | 1797010266980876288 |
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| author | Lim , Yen Ruen |
| author_facet | Lim , Yen Ruen |
| author_sort | Lim , Yen Ruen |
| collection | USM |
| description | Secure data transfer has been the most challenging task for Internet of Things (IoT) devices. Data integrity must be ensured before and after the data transmission. Cryptographic hash functions are generally the basis of a secure network and used for data integrity verification. Cryptographic hash functions carried out processes such as identity verification, file integrity checking, secure key passing, and source code version control. Among all of the cryptography measures, Secure Hash Algorithm 3 (SHA-3) is the newest and secure cryptographic hash algorithm in the current electronic industry. In the previous Intel Microelectronic SHA-3 design, the synthesized area of the design is large due to many intermediate states and logics of the step mapping functions. The objective of this project is to design a synthesizable SHA-3 with 256-bits hash output and 1600-bits state array with lower area compared to Intel Microelectronic SHA-3. This research implements the SHA-3 in ways such that all the step mapping algorithms are logically combined to only use the input lanes of the state array to eliminate the intermediate logics and reduces the area size. Functionality verification is done using the test case provided by National Institute Standards and Technology (NIST). Two squeezing phases are tested to ensure the functionality of design. Final design of SHA-3 in this research can achieve area reduction by 12.57%, the cell count reduction by 24.35%, the critical path length reduction by 18.84%, and reduction of the clock cycles needed to generate the hash output by 75%. In conclusion, the SHA-3 with smaller area and higher performance has been designed and is possible to cater the needs of IoT application. |
| first_indexed | 2024-03-06T15:17:21Z |
| format | Thesis |
| id | usm.eprints-39583 |
| institution | Universiti Sains Malaysia |
| language | English |
| last_indexed | 2024-03-06T15:17:21Z |
| publishDate | 2017 |
| record_format | dspace |
| spelling | usm.eprints-395832019-04-12T05:25:07Z http://eprints.usm.my/39583/ Rtl Implementation Of Secure Hash Algorithm 3 (Sha-3) Towards Smaller Area Lim , Yen Ruen TK1-9971 Electrical engineering. Electronics. Nuclear engineering Secure data transfer has been the most challenging task for Internet of Things (IoT) devices. Data integrity must be ensured before and after the data transmission. Cryptographic hash functions are generally the basis of a secure network and used for data integrity verification. Cryptographic hash functions carried out processes such as identity verification, file integrity checking, secure key passing, and source code version control. Among all of the cryptography measures, Secure Hash Algorithm 3 (SHA-3) is the newest and secure cryptographic hash algorithm in the current electronic industry. In the previous Intel Microelectronic SHA-3 design, the synthesized area of the design is large due to many intermediate states and logics of the step mapping functions. The objective of this project is to design a synthesizable SHA-3 with 256-bits hash output and 1600-bits state array with lower area compared to Intel Microelectronic SHA-3. This research implements the SHA-3 in ways such that all the step mapping algorithms are logically combined to only use the input lanes of the state array to eliminate the intermediate logics and reduces the area size. Functionality verification is done using the test case provided by National Institute Standards and Technology (NIST). Two squeezing phases are tested to ensure the functionality of design. Final design of SHA-3 in this research can achieve area reduction by 12.57%, the cell count reduction by 24.35%, the critical path length reduction by 18.84%, and reduction of the clock cycles needed to generate the hash output by 75%. In conclusion, the SHA-3 with smaller area and higher performance has been designed and is possible to cater the needs of IoT application. 2017 Thesis NonPeerReviewed application/pdf en http://eprints.usm.my/39583/1/LIM_YEN_RUEN_24_Pages.pdf Lim , Yen Ruen (2017) Rtl Implementation Of Secure Hash Algorithm 3 (Sha-3) Towards Smaller Area. Masters thesis, Universiti Sains Malaysia. |
| spellingShingle | TK1-9971 Electrical engineering. Electronics. Nuclear engineering Lim , Yen Ruen Rtl Implementation Of Secure Hash Algorithm 3 (Sha-3) Towards Smaller Area |
| title | Rtl Implementation Of Secure Hash Algorithm 3 (Sha-3) Towards Smaller Area |
| title_full | Rtl Implementation Of Secure Hash Algorithm 3 (Sha-3) Towards Smaller Area |
| title_fullStr | Rtl Implementation Of Secure Hash Algorithm 3 (Sha-3) Towards Smaller Area |
| title_full_unstemmed | Rtl Implementation Of Secure Hash Algorithm 3 (Sha-3) Towards Smaller Area |
| title_short | Rtl Implementation Of Secure Hash Algorithm 3 (Sha-3) Towards Smaller Area |
| title_sort | rtl implementation of secure hash algorithm 3 sha 3 towards smaller area |
| topic | TK1-9971 Electrical engineering. Electronics. Nuclear engineering |
| url | http://eprints.usm.my/39583/1/LIM_YEN_RUEN_24_Pages.pdf |
| work_keys_str_mv | AT limyenruen rtlimplementationofsecurehashalgorithm3sha3towardssmallerarea |