Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect
As the process technology advances, transistor size shrinks and more intellectual properties (IPs) are integrated onto chip. In order to accommodate the current complex functionalities as well as improving the performance of design, integrated circuit (IC) architecture has encouraged the integration...
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| Format: | Thesis |
| Language: | English |
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2016
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| Online Access: | http://eprints.usm.my/41312/1/CHIEW_CHONG_GIAP_24_Pages.pdf |
| _version_ | 1825834405847891968 |
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| author | Chiew , Chong Giap |
| author_facet | Chiew , Chong Giap |
| author_sort | Chiew , Chong Giap |
| collection | USM |
| description | As the process technology advances, transistor size shrinks and more intellectual properties (IPs) are integrated onto chip. In order to accommodate the current complex functionalities as well as improving the performance of design, integrated circuit (IC) architecture has encouraged the integration of multiple die on a single chip. Communication between die requires full network-on-chip (NoC) which is area intensive. In deep sub-micron process nodes, high speed signaling between multiple die becomes one of the main challenges in multidie chip design. Methods to increase the routability have been proposed as the use of parallel interconnect appears to be the bottleneck of high speed multidie communication. Conversion of parallel data bits into serial data streams before transmission effectively reduced the number of wires required for the interconnect. Synchronous serial transmission requires large design dimension and power hungry auxiliary blocks for synchronization between the transmitted data and clock signals. This is avoided with the implementation of self-timed transmission scheme which eliminates the need to transmit the clock signal in a separate wire. This research is conducted to develop a reusable, scalable and configurable clockless version of SerDes system as the interconnect between multiple die. The proposed design achieves a data rate of 2 Gbps small area 38.71 μm² with architectural simplicity with 308 transistor count and low power consumption of 1.10 mW. |
| first_indexed | 2024-03-06T15:22:15Z |
| format | Thesis |
| id | usm.eprints-41312 |
| institution | Universiti Sains Malaysia |
| language | English |
| last_indexed | 2024-03-06T15:22:15Z |
| publishDate | 2016 |
| record_format | dspace |
| spelling | usm.eprints-413122018-08-14T04:08:47Z http://eprints.usm.my/41312/ Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect Chiew , Chong Giap TK7800-8360 Electronics As the process technology advances, transistor size shrinks and more intellectual properties (IPs) are integrated onto chip. In order to accommodate the current complex functionalities as well as improving the performance of design, integrated circuit (IC) architecture has encouraged the integration of multiple die on a single chip. Communication between die requires full network-on-chip (NoC) which is area intensive. In deep sub-micron process nodes, high speed signaling between multiple die becomes one of the main challenges in multidie chip design. Methods to increase the routability have been proposed as the use of parallel interconnect appears to be the bottleneck of high speed multidie communication. Conversion of parallel data bits into serial data streams before transmission effectively reduced the number of wires required for the interconnect. Synchronous serial transmission requires large design dimension and power hungry auxiliary blocks for synchronization between the transmitted data and clock signals. This is avoided with the implementation of self-timed transmission scheme which eliminates the need to transmit the clock signal in a separate wire. This research is conducted to develop a reusable, scalable and configurable clockless version of SerDes system as the interconnect between multiple die. The proposed design achieves a data rate of 2 Gbps small area 38.71 μm² with architectural simplicity with 308 transistor count and low power consumption of 1.10 mW. 2016 Thesis NonPeerReviewed application/pdf en http://eprints.usm.my/41312/1/CHIEW_CHONG_GIAP_24_Pages.pdf Chiew , Chong Giap (2016) Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect. Masters thesis, Universiti Sains Malaysia. |
| spellingShingle | TK7800-8360 Electronics Chiew , Chong Giap Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect |
| title | Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect
|
| title_full | Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect
|
| title_fullStr | Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect
|
| title_full_unstemmed | Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect
|
| title_short | Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect
|
| title_sort | prelayout design of configurable serdes for high speed signaling in multidie interconnect |
| topic | TK7800-8360 Electronics |
| url | http://eprints.usm.my/41312/1/CHIEW_CHONG_GIAP_24_Pages.pdf |
| work_keys_str_mv | AT chiewchonggiap prelayoutdesignofconfigurableserdesforhighspeedsignalinginmultidieinterconnect |