Fpga-Based Accelerator For The Identification Of Finger Vein Pattern Via K-Nearest Centroid Neighbors

In recent years, finger vein recognition has emerged as a promising biometric technology due to the fact that each person in this world has unique finger vein pattern. Over the past few years, various finger vein recognition algorithms and techniques have been proposed by researchers and scholars. T...

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Manylion Llyfryddiaeth
Prif Awdur: Yew , Tze Ee
Fformat: Traethawd Ymchwil
Iaith:English
Cyhoeddwyd: 2016
Pynciau:
Mynediad Ar-lein:http://eprints.usm.my/41321/1/YEW_TZE_EE_24_Pages.pdf
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author Yew , Tze Ee
author_facet Yew , Tze Ee
author_sort Yew , Tze Ee
collection USM
description In recent years, finger vein recognition has emerged as a promising biometric technology due to the fact that each person in this world has unique finger vein pattern. Over the past few years, various finger vein recognition algorithms and techniques have been proposed by researchers and scholars. The challenge of finger vein recognition in becoming mainstream biometric technology is the processing time of recognition. As almost all finger vein recognition algorithms were implemented using software such as MATLAB which is based on general-purpose processor, the processing speed become the bottleneck of the development of finger vein recognition. In order to increase the processing, this thesis introduces an architecture for finger vein recognition based on K-Nearest Centroid Neighbors (KNCN) classifier implemented on Field Programmable Gate Array (FPGA). KNCN is a type of classification technique in image processing which involves calculation of centroid and sorting of K-nearest centroid neighbors. FPGA enables parallel computation in contrasts to serial computation in general processor. The proposed architecture is written in Verilog Hardware Description Language (HDL) and programmed into Altera Development and Educational Board, DE2-115 through Quartus II 15.0. An image database which consists of 80 finger vein classes has been used to evaluate the accuracy and processing time of the proposed architecture. Experimental results showed that the processing time of the hardware architecture for KNCN classifier implemented on FPGA for one testing image is 4.98 ms, which is 9 times faster than software implementation of KNCN classifier. The accuracy of the hardware architecture is 77% which is slightly lower than the accuracy in MATLAB. In conclusion, the finger vein identification hardware architecture based on KNCN classifier is successfully implemented on an FPGA board with faster processing time as compared with software-based implementation of KNCN classifier in MATLAB.
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spelling usm.eprints-413212018-08-14T07:46:46Z http://eprints.usm.my/41321/ Fpga-Based Accelerator For The Identification Of Finger Vein Pattern Via K-Nearest Centroid Neighbors Yew , Tze Ee TK7800-8360 Electronics In recent years, finger vein recognition has emerged as a promising biometric technology due to the fact that each person in this world has unique finger vein pattern. Over the past few years, various finger vein recognition algorithms and techniques have been proposed by researchers and scholars. The challenge of finger vein recognition in becoming mainstream biometric technology is the processing time of recognition. As almost all finger vein recognition algorithms were implemented using software such as MATLAB which is based on general-purpose processor, the processing speed become the bottleneck of the development of finger vein recognition. In order to increase the processing, this thesis introduces an architecture for finger vein recognition based on K-Nearest Centroid Neighbors (KNCN) classifier implemented on Field Programmable Gate Array (FPGA). KNCN is a type of classification technique in image processing which involves calculation of centroid and sorting of K-nearest centroid neighbors. FPGA enables parallel computation in contrasts to serial computation in general processor. The proposed architecture is written in Verilog Hardware Description Language (HDL) and programmed into Altera Development and Educational Board, DE2-115 through Quartus II 15.0. An image database which consists of 80 finger vein classes has been used to evaluate the accuracy and processing time of the proposed architecture. Experimental results showed that the processing time of the hardware architecture for KNCN classifier implemented on FPGA for one testing image is 4.98 ms, which is 9 times faster than software implementation of KNCN classifier. The accuracy of the hardware architecture is 77% which is slightly lower than the accuracy in MATLAB. In conclusion, the finger vein identification hardware architecture based on KNCN classifier is successfully implemented on an FPGA board with faster processing time as compared with software-based implementation of KNCN classifier in MATLAB. 2016 Thesis NonPeerReviewed application/pdf en http://eprints.usm.my/41321/1/YEW_TZE_EE_24_Pages.pdf Yew , Tze Ee (2016) Fpga-Based Accelerator For The Identification Of Finger Vein Pattern Via K-Nearest Centroid Neighbors. Masters thesis, Universiti Sains Malaysia.
spellingShingle TK7800-8360 Electronics
Yew , Tze Ee
Fpga-Based Accelerator For The Identification Of Finger Vein Pattern Via K-Nearest Centroid Neighbors
title Fpga-Based Accelerator For The Identification Of Finger Vein Pattern Via K-Nearest Centroid Neighbors
title_full Fpga-Based Accelerator For The Identification Of Finger Vein Pattern Via K-Nearest Centroid Neighbors
title_fullStr Fpga-Based Accelerator For The Identification Of Finger Vein Pattern Via K-Nearest Centroid Neighbors
title_full_unstemmed Fpga-Based Accelerator For The Identification Of Finger Vein Pattern Via K-Nearest Centroid Neighbors
title_short Fpga-Based Accelerator For The Identification Of Finger Vein Pattern Via K-Nearest Centroid Neighbors
title_sort fpga based accelerator for the identification of finger vein pattern via k nearest centroid neighbors
topic TK7800-8360 Electronics
url http://eprints.usm.my/41321/1/YEW_TZE_EE_24_Pages.pdf
work_keys_str_mv AT yewtzeee fpgabasedacceleratorfortheidentificationoffingerveinpatternviaknearestcentroidneighbors