Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform

Hardware/Software (HW/SW) co-design approaches become prospective choice due to its real time operation since these solutions are so flexible that cover extensive complicated systems and reduce time from design to market. Hybrid digital signal processors (DSPs), field programmable gate arrays (FPGAs...

Full description

Bibliographic Details
Main Author: Hamza, Ekhlas Kadhum
Format: Thesis
Language:English
Published: 2011
Subjects:
Online Access:http://eprints.usm.my/43261/1/EKHLAS%20KADHUM%20HAMZA.pdf
_version_ 1825834767243804672
author Hamza, Ekhlas Kadhum
author_facet Hamza, Ekhlas Kadhum
author_sort Hamza, Ekhlas Kadhum
collection USM
description Hardware/Software (HW/SW) co-design approaches become prospective choice due to its real time operation since these solutions are so flexible that cover extensive complicated systems and reduce time from design to market. Hybrid digital signal processors (DSPs), field programmable gate arrays (FPGAs) and general-purpose processors (GPPs) designs are viable solution for software defined radio (SDR) technology. This thesis demonstrates a practical design and implementation procedure for building a useful, efficient and flexible model of a bit error rate tester (BERT) on physical layer for UHF-band of the digital transceivers by using new architecture in Multi-Core Software-Defined Radio
first_indexed 2024-03-06T15:27:38Z
format Thesis
id usm.eprints-43261
institution Universiti Sains Malaysia
language English
last_indexed 2024-03-06T15:27:38Z
publishDate 2011
record_format dspace
spelling usm.eprints-432612019-04-12T05:26:29Z http://eprints.usm.my/43261/ Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform Hamza, Ekhlas Kadhum TK1-9971 Electrical engineering. Electronics. Nuclear engineering Hardware/Software (HW/SW) co-design approaches become prospective choice due to its real time operation since these solutions are so flexible that cover extensive complicated systems and reduce time from design to market. Hybrid digital signal processors (DSPs), field programmable gate arrays (FPGAs) and general-purpose processors (GPPs) designs are viable solution for software defined radio (SDR) technology. This thesis demonstrates a practical design and implementation procedure for building a useful, efficient and flexible model of a bit error rate tester (BERT) on physical layer for UHF-band of the digital transceivers by using new architecture in Multi-Core Software-Defined Radio 2011-10 Thesis NonPeerReviewed application/pdf en http://eprints.usm.my/43261/1/EKHLAS%20KADHUM%20HAMZA.pdf Hamza, Ekhlas Kadhum (2011) Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform. PhD thesis, Universiti Sains Malaysia.
spellingShingle TK1-9971 Electrical engineering. Electronics. Nuclear engineering
Hamza, Ekhlas Kadhum
Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform
title Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform
title_full Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform
title_fullStr Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform
title_full_unstemmed Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform
title_short Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform
title_sort development and implementation of a new technique for bert bit error rate tester using sdr platform
topic TK1-9971 Electrical engineering. Electronics. Nuclear engineering
url http://eprints.usm.my/43261/1/EKHLAS%20KADHUM%20HAMZA.pdf
work_keys_str_mv AT hamzaekhlaskadhum developmentandimplementationofanewtechniqueforbertbiterrorratetesterusingsdrplatform