Automated Placement Of A Transistor Pair For Analogue
The performances of analogue circuits are affected by surrounding parameters such as levels of noise, thermal gradients of a circuit, and parasitic effects from both resistive and capacitive part. As there are no effective approaches to handle these analogue constraints as mentioned above, the focus...
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| Format: | Thesis |
| Language: | English |
| Published: |
2012
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| Online Access: | http://eprints.usm.my/43926/1/Saravanan%20Balakrishnan24.pdf |
| _version_ | 1825834877632643072 |
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| author | Balakrishnan, Saravanan |
| author_facet | Balakrishnan, Saravanan |
| author_sort | Balakrishnan, Saravanan |
| collection | USM |
| description | The performances of analogue circuits are affected by surrounding parameters such as levels of noise, thermal gradients of a circuit, and parasitic effects from both resistive and capacitive part. As there are no effective approaches to handle these analogue constraints as mentioned above, the focuses to develop IC design tools are bended towards digital circuits. The purpose of this research is to introduce a complete methodology for transistor pair placement for analogue layout using a concept of cells and arrays based on migration and reuse. The entire process consists of Standard Cell Generation to produce standard cell for analogue circuits, Matching Generator with array alignment to generate transistor matching of common-centroid arrangement, and Auto Routing for global routing. The methodology is translated into automation by a graphical user interface to render a fully functional layout designs in a few steps and fraction of time. This research describes such a system in obtaining a layout that can be configured like a set of building blocks that meets all design specifications. In comparison to all the different approaches that have been discussed and analysed prior to this research, a new design flow for analogue layout combined with automation is constructed by considering transistor matching as a constraint. |
| first_indexed | 2024-03-06T15:29:17Z |
| format | Thesis |
| id | usm.eprints-43926 |
| institution | Universiti Sains Malaysia |
| language | English |
| last_indexed | 2024-03-06T15:29:17Z |
| publishDate | 2012 |
| record_format | dspace |
| spelling | usm.eprints-439262019-04-12T05:26:20Z http://eprints.usm.my/43926/ Automated Placement Of A Transistor Pair For Analogue Balakrishnan, Saravanan TK1-9971 Electrical engineering. Electronics. Nuclear engineering The performances of analogue circuits are affected by surrounding parameters such as levels of noise, thermal gradients of a circuit, and parasitic effects from both resistive and capacitive part. As there are no effective approaches to handle these analogue constraints as mentioned above, the focuses to develop IC design tools are bended towards digital circuits. The purpose of this research is to introduce a complete methodology for transistor pair placement for analogue layout using a concept of cells and arrays based on migration and reuse. The entire process consists of Standard Cell Generation to produce standard cell for analogue circuits, Matching Generator with array alignment to generate transistor matching of common-centroid arrangement, and Auto Routing for global routing. The methodology is translated into automation by a graphical user interface to render a fully functional layout designs in a few steps and fraction of time. This research describes such a system in obtaining a layout that can be configured like a set of building blocks that meets all design specifications. In comparison to all the different approaches that have been discussed and analysed prior to this research, a new design flow for analogue layout combined with automation is constructed by considering transistor matching as a constraint. 2012-05 Thesis NonPeerReviewed application/pdf en http://eprints.usm.my/43926/1/Saravanan%20Balakrishnan24.pdf Balakrishnan, Saravanan (2012) Automated Placement Of A Transistor Pair For Analogue. Masters thesis, Universiti Sains Malaysia. |
| spellingShingle | TK1-9971 Electrical engineering. Electronics. Nuclear engineering Balakrishnan, Saravanan Automated Placement Of A Transistor Pair For Analogue |
| title | Automated Placement Of A Transistor Pair For Analogue |
| title_full | Automated Placement Of A Transistor Pair For Analogue |
| title_fullStr | Automated Placement Of A Transistor Pair For Analogue |
| title_full_unstemmed | Automated Placement Of A Transistor Pair For Analogue |
| title_short | Automated Placement Of A Transistor Pair For Analogue |
| title_sort | automated placement of a transistor pair for analogue |
| topic | TK1-9971 Electrical engineering. Electronics. Nuclear engineering |
| url | http://eprints.usm.my/43926/1/Saravanan%20Balakrishnan24.pdf |
| work_keys_str_mv | AT balakrishnansaravanan automatedplacementofatransistorpairforanalogue |