A 2x2 bit multiplier using hybrid 13 t full adder with vedic mathematics method
Various arithmetic circuits such as multipliers require full adder (FA) as the main block for the circuit to operate. Speed and energy consumption become very vital in design consideration for a low power adder. In this paper, a 2x2 bit Vedic multiplier using hybrid full adder (HFA) with 13 transist...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Penerbit UTHM
2018
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| Subjects: | |
| Online Access: | http://eprints.uthm.edu.my/5690/1/AJ%202018%20%28307%29.pdf |