VHDL implementation of pipelined DLX microprocessor
The 32-bit load/store DLX processor architecture is a generic RISC processor designed by Hennessy and Patterson for pedagogical purposes. The DLX processor design abstracts many features of general-purpose commercial processors, and is a well-understood computer architecture, providing a good archit...
| Main Author: | |
|---|---|
| Format: | Thesis |
| Language: | English |
| Published: |
2008
|
| Subjects: | |
| Online Access: | http://eprints.utm.my/11462/1/IgnatiusEdmondAnthonyFKE2008.pdf |
| _version_ | 1796854885551964160 |
|---|---|
| author | Anthony, Ignatius Edmond |
| author_facet | Anthony, Ignatius Edmond |
| author_sort | Anthony, Ignatius Edmond |
| collection | ePrints |
| description | The 32-bit load/store DLX processor architecture is a generic RISC processor designed by Hennessy and Patterson for pedagogical purposes. The DLX processor design abstracts many features of general-purpose commercial processors, and is a well-understood computer architecture, providing a good architectural model for study, not only because of the popularity of this type of machine, but also because it is easy to understand. Utilizing open source hardware such as the DLX core yields the apparent advantage of free-for-all distribution as well as having source codes that are is available and open, allowing for source code modification at-will. This project aims to continue previous work on integration of the DLX core by adding instruction pipelining which was excluded from the previous project’s scope due to complexity and time limitations. Instruction execution speedup and performance was left on the table to be dealt with in future work. Since the DLX microprocessor was, by nature, a 5-stage pipelined microprocessor, it can be expected that the core’s performance on instruction execution can be sped up with a pipeline implementation. Comparison between the non-pipelined and pipelined DLX were also performed to verify this instruction execution speedup expectation. |
| first_indexed | 2024-03-05T18:20:41Z |
| format | Thesis |
| id | utm.eprints-11462 |
| institution | Universiti Teknologi Malaysia - ePrints |
| language | English |
| last_indexed | 2024-03-05T18:20:41Z |
| publishDate | 2008 |
| record_format | dspace |
| spelling | utm.eprints-114622018-07-23T05:37:13Z http://eprints.utm.my/11462/ VHDL implementation of pipelined DLX microprocessor Anthony, Ignatius Edmond QA75 Electronic computers. Computer science TK Electrical engineering. Electronics Nuclear engineering The 32-bit load/store DLX processor architecture is a generic RISC processor designed by Hennessy and Patterson for pedagogical purposes. The DLX processor design abstracts many features of general-purpose commercial processors, and is a well-understood computer architecture, providing a good architectural model for study, not only because of the popularity of this type of machine, but also because it is easy to understand. Utilizing open source hardware such as the DLX core yields the apparent advantage of free-for-all distribution as well as having source codes that are is available and open, allowing for source code modification at-will. This project aims to continue previous work on integration of the DLX core by adding instruction pipelining which was excluded from the previous project’s scope due to complexity and time limitations. Instruction execution speedup and performance was left on the table to be dealt with in future work. Since the DLX microprocessor was, by nature, a 5-stage pipelined microprocessor, it can be expected that the core’s performance on instruction execution can be sped up with a pipeline implementation. Comparison between the non-pipelined and pipelined DLX were also performed to verify this instruction execution speedup expectation. 2008-05 Thesis NonPeerReviewed application/pdf en http://eprints.utm.my/11462/1/IgnatiusEdmondAnthonyFKE2008.pdf Anthony, Ignatius Edmond (2008) VHDL implementation of pipelined DLX microprocessor. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering. |
| spellingShingle | QA75 Electronic computers. Computer science TK Electrical engineering. Electronics Nuclear engineering Anthony, Ignatius Edmond VHDL implementation of pipelined DLX microprocessor |
| title | VHDL implementation of pipelined DLX microprocessor |
| title_full | VHDL implementation of pipelined DLX microprocessor |
| title_fullStr | VHDL implementation of pipelined DLX microprocessor |
| title_full_unstemmed | VHDL implementation of pipelined DLX microprocessor |
| title_short | VHDL implementation of pipelined DLX microprocessor |
| title_sort | vhdl implementation of pipelined dlx microprocessor |
| topic | QA75 Electronic computers. Computer science TK Electrical engineering. Electronics Nuclear engineering |
| url | http://eprints.utm.my/11462/1/IgnatiusEdmondAnthonyFKE2008.pdf |
| work_keys_str_mv | AT anthonyignatiusedmond vhdlimplementationofpipelineddlxmicroprocessor |