Modeling of a ladder logic processor for high performance programmable logic controller
Today, programmable logic controllers (PLCs) is the dominant technology deployed in control automation systems in modern factories. The main modeling method of the PLC is based on ladder logic diagrams (LLDs). However, as a system gets more complex, LLD implementations poses a stumbling block in the...
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Format: | Book Section |
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Institute of Electrical and Electronics Engineers
2009
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author | Aspar, Zulfakar Khalil-Hani, Mohamed |
author_facet | Aspar, Zulfakar Khalil-Hani, Mohamed |
author_sort | Aspar, Zulfakar |
collection | ePrints |
description | Today, programmable logic controllers (PLCs) is the dominant technology deployed in control automation systems in modern factories. The main modeling method of the PLC is based on ladder logic diagrams (LLDs). However, as a system gets more complex, LLD implementations poses a stumbling block in the design of more complex and real-time PLCs. Consequently, in this paper, a novel architecture for a high performance LLD implementation, which we call the Ladder Logic Processor, is proposed. In the proposed architecture, each computation of the underlying ladder logic is performed at a fixed number of clock cycles per ladder rung, regardless of the number of steps involved. Notwithstanding, the technique maintains the existing LLD paradigm where every rung is processed sequentially. The LLDs are targeted for implementation in Field Programmable Gate Arrays (FPGAs). Experimental work performed to evaluate the performance of the proposed architecture shows promising results. |
first_indexed | 2024-03-05T18:24:40Z |
format | Book Section |
id | utm.eprints-12969 |
institution | Universiti Teknologi Malaysia - ePrints |
last_indexed | 2024-03-05T18:24:40Z |
publishDate | 2009 |
publisher | Institute of Electrical and Electronics Engineers |
record_format | dspace |
spelling | utm.eprints-129692011-07-07T09:45:47Z http://eprints.utm.my/12969/ Modeling of a ladder logic processor for high performance programmable logic controller Aspar, Zulfakar Khalil-Hani, Mohamed TK Electrical engineering. Electronics Nuclear engineering Today, programmable logic controllers (PLCs) is the dominant technology deployed in control automation systems in modern factories. The main modeling method of the PLC is based on ladder logic diagrams (LLDs). However, as a system gets more complex, LLD implementations poses a stumbling block in the design of more complex and real-time PLCs. Consequently, in this paper, a novel architecture for a high performance LLD implementation, which we call the Ladder Logic Processor, is proposed. In the proposed architecture, each computation of the underlying ladder logic is performed at a fixed number of clock cycles per ladder rung, regardless of the number of steps involved. Notwithstanding, the technique maintains the existing LLD paradigm where every rung is processed sequentially. The LLDs are targeted for implementation in Field Programmable Gate Arrays (FPGAs). Experimental work performed to evaluate the performance of the proposed architecture shows promising results. Institute of Electrical and Electronics Engineers 2009 Book Section PeerReviewed Aspar, Zulfakar and Khalil-Hani, Mohamed (2009) Modeling of a ladder logic processor for high performance programmable logic controller. In: Proceedings - 2009 3rd Asia International Conference on Modelling and Simulation, AMS 2009. Institute of Electrical and Electronics Engineers, New York, 572 -577. ISBN 978-076953648-4 http://dx.doi.org/10.1109/AMS.2009.83 doi:10.1109/AMS.2009.83 |
spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Aspar, Zulfakar Khalil-Hani, Mohamed Modeling of a ladder logic processor for high performance programmable logic controller |
title | Modeling of a ladder logic processor for high performance programmable logic controller |
title_full | Modeling of a ladder logic processor for high performance programmable logic controller |
title_fullStr | Modeling of a ladder logic processor for high performance programmable logic controller |
title_full_unstemmed | Modeling of a ladder logic processor for high performance programmable logic controller |
title_short | Modeling of a ladder logic processor for high performance programmable logic controller |
title_sort | modeling of a ladder logic processor for high performance programmable logic controller |
topic | TK Electrical engineering. Electronics Nuclear engineering |
work_keys_str_mv | AT asparzulfakar modelingofaladderlogicprocessorforhighperformanceprogrammablelogiccontroller AT khalilhanimohamed modelingofaladderlogicprocessorforhighperformanceprogrammablelogiccontroller |