Vertical double gate MOSFET for nanoscale device with fully depleted feature

A fully depleted vertical double gate MOSFET device was revealed with the implementation of oblique rotating implantation (ORI) method in 25 nm silicon pillar thickness. Several devices with various gate lengths (20 - 100 nm) were simulated and evaluated using virtual wafer tool. The implication of...

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Main Authors: Riyadi, Munawar A., Saad, Ismail, Ahmadi, M. Taghi, Ismail, Razali, Rusop, Mohamad, Soga, Tetsuo
Format: Book Section
Published: Institute of Electrical and Electronics Engineers 2009
Subjects:
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author Riyadi, Munawar A.
Saad, Ismail
Ahmadi, M. Taghi
Ismail, Razali
Rusop, Mohamad
Soga, Tetsuo
author_facet Riyadi, Munawar A.
Saad, Ismail
Ahmadi, M. Taghi
Ismail, Razali
Rusop, Mohamad
Soga, Tetsuo
author_sort Riyadi, Munawar A.
collection ePrints
description A fully depleted vertical double gate MOSFET device was revealed with the implementation of oblique rotating implantation (ORI) method in 25 nm silicon pillar thickness. Several devices with various gate lengths (20 - 100 nm) were simulated and evaluated using virtual wafer tool. The implication of gate length reduction on the short channel effect (SCE) shows considerable advantages with higher current drives at lower gate length, while the low subthreshold swing could balance the threshold voltage roll-off in the term of increasing power consumption. As a result, the drive current and also SCE controllability will be a benefit in the fully depleted device.
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institution Universiti Teknologi Malaysia - ePrints
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publisher Institute of Electrical and Electronics Engineers
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spelling utm.eprints-131822011-07-20T08:56:47Z http://eprints.utm.my/13182/ Vertical double gate MOSFET for nanoscale device with fully depleted feature Riyadi, Munawar A. Saad, Ismail Ahmadi, M. Taghi Ismail, Razali Rusop, Mohamad Soga, Tetsuo TK Electrical engineering. Electronics Nuclear engineering A fully depleted vertical double gate MOSFET device was revealed with the implementation of oblique rotating implantation (ORI) method in 25 nm silicon pillar thickness. Several devices with various gate lengths (20 - 100 nm) were simulated and evaluated using virtual wafer tool. The implication of gate length reduction on the short channel effect (SCE) shows considerable advantages with higher current drives at lower gate length, while the low subthreshold swing could balance the threshold voltage roll-off in the term of increasing power consumption. As a result, the drive current and also SCE controllability will be a benefit in the fully depleted device. Institute of Electrical and Electronics Engineers 2009 Book Section PeerReviewed Riyadi, Munawar A. and Saad, Ismail and Ahmadi, M. Taghi and Ismail, Razali and Rusop, Mohamad and Soga, Tetsuo (2009) Vertical double gate MOSFET for nanoscale device with fully depleted feature. In: AIP Conference Proceedings. Institute of Electrical and Electronics Engineers, New York, pp. 248-252. ISBN 978-073540673-5 http://dx.doi.org/10.1063/1.3160141 doi:10.1063/1.3160141
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Riyadi, Munawar A.
Saad, Ismail
Ahmadi, M. Taghi
Ismail, Razali
Rusop, Mohamad
Soga, Tetsuo
Vertical double gate MOSFET for nanoscale device with fully depleted feature
title Vertical double gate MOSFET for nanoscale device with fully depleted feature
title_full Vertical double gate MOSFET for nanoscale device with fully depleted feature
title_fullStr Vertical double gate MOSFET for nanoscale device with fully depleted feature
title_full_unstemmed Vertical double gate MOSFET for nanoscale device with fully depleted feature
title_short Vertical double gate MOSFET for nanoscale device with fully depleted feature
title_sort vertical double gate mosfet for nanoscale device with fully depleted feature
topic TK Electrical engineering. Electronics Nuclear engineering
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