An extended class of acyclically testable circuits
This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose test generation complexity is equivalent to that of the acyclic sequential circuits. We also present a test generation proce...
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| Format: | Conference or Workshop Item |
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2007
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| _version_ | 1796855294307860480 |
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| author | Oka, Nobuyo Chia, Yee Ooi Ichihara, Hideyuki Inoue, Tomoo Fujiwara, Hideo |
| author_facet | Oka, Nobuyo Chia, Yee Ooi Ichihara, Hideyuki Inoue, Tomoo Fujiwara, Hideo |
| author_sort | Oka, Nobuyo |
| collection | ePrints |
| description | This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose test generation complexity is equivalent to that of the acyclic sequential circuits. We also present a test generation procedure for acyclically testable sequential circuits and elaborate a design-for-test (DFT) method to augment an arbitrary sequential circuit into an acyclically testable sequential circuit. |
| first_indexed | 2024-03-05T18:26:30Z |
| format | Conference or Workshop Item |
| id | utm.eprints-13732 |
| institution | Universiti Teknologi Malaysia - ePrints |
| last_indexed | 2024-03-05T18:26:30Z |
| publishDate | 2007 |
| record_format | dspace |
| spelling | utm.eprints-137322017-09-14T04:03:17Z http://eprints.utm.my/13732/ An extended class of acyclically testable circuits Oka, Nobuyo Chia, Yee Ooi Ichihara, Hideyuki Inoue, Tomoo Fujiwara, Hideo TK Electrical engineering. Electronics Nuclear engineering This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose test generation complexity is equivalent to that of the acyclic sequential circuits. We also present a test generation procedure for acyclically testable sequential circuits and elaborate a design-for-test (DFT) method to augment an arbitrary sequential circuit into an acyclically testable sequential circuit. 2007 Conference or Workshop Item PeerReviewed Oka, Nobuyo and Chia, Yee Ooi and Ichihara, Hideyuki and Inoue, Tomoo and Fujiwara, Hideo (2007) An extended class of acyclically testable circuits. In: IEEE 8th Workshop on RTL and High Level Testing, 2007, Beijing, China. |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Oka, Nobuyo Chia, Yee Ooi Ichihara, Hideyuki Inoue, Tomoo Fujiwara, Hideo An extended class of acyclically testable circuits |
| title | An extended class of acyclically testable circuits |
| title_full | An extended class of acyclically testable circuits |
| title_fullStr | An extended class of acyclically testable circuits |
| title_full_unstemmed | An extended class of acyclically testable circuits |
| title_short | An extended class of acyclically testable circuits |
| title_sort | extended class of acyclically testable circuits |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
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