Design and simulation analysis of nanoscale vertical MOSFET technology
Design consideration of vertical MOSFET with double gate structure on each side of insulating pillar for nanodevice applications is presented. The body doping effect on vertical channel for channel length, Lg = 50 nm and analyzing its effect towards such small devices was successfully performed. The...
| Main Authors: | , , , |
|---|---|
| Format: | Conference or Workshop Item |
| Published: |
2009
|
| Subjects: |
| _version_ | 1796855476962459648 |
|---|---|
| author | Saad, Ismail Mohd. Ali Lee, Razak A. Riyadi, Munawar Ismail, Razali |
| author_facet | Saad, Ismail Mohd. Ali Lee, Razak A. Riyadi, Munawar Ismail, Razali |
| author_sort | Saad, Ismail |
| collection | ePrints |
| description | Design consideration of vertical MOSFET with double gate structure on each side of insulating pillar for nanodevice applications is presented. The body doping effect on vertical channel for channel length, Lg = 50 nm and analyzing its effect towards such small devices was successfully performed. The analysis continued with the comparative investigation of device performance with conventional planar MOSFET as scaling Lg down to 50 nm. The final part evaluates the innovative design of incorporating dielectric pocket (DP) on top of vertical MOSFET turret with comprehensive device performance analysis as compared to standard vertical MOSFET in nanoscale realm. An optimized body doping for enhanced performance of vertical MOSFET was revealed. The vicinity of DP near the drain end is found to reduce the charge sharing effects between source and drain that gives better gate control of the depletion region for short channel effect (SCE) suppression in nanodevice structure. |
| first_indexed | 2024-03-05T18:29:04Z |
| format | Conference or Workshop Item |
| id | utm.eprints-15035 |
| institution | Universiti Teknologi Malaysia - ePrints |
| last_indexed | 2024-03-05T18:29:04Z |
| publishDate | 2009 |
| record_format | dspace |
| spelling | utm.eprints-150352020-07-20T01:23:53Z http://eprints.utm.my/15035/ Design and simulation analysis of nanoscale vertical MOSFET technology Saad, Ismail Mohd. Ali Lee, Razak A. Riyadi, Munawar Ismail, Razali TK Electrical engineering. Electronics Nuclear engineering Design consideration of vertical MOSFET with double gate structure on each side of insulating pillar for nanodevice applications is presented. The body doping effect on vertical channel for channel length, Lg = 50 nm and analyzing its effect towards such small devices was successfully performed. The analysis continued with the comparative investigation of device performance with conventional planar MOSFET as scaling Lg down to 50 nm. The final part evaluates the innovative design of incorporating dielectric pocket (DP) on top of vertical MOSFET turret with comprehensive device performance analysis as compared to standard vertical MOSFET in nanoscale realm. An optimized body doping for enhanced performance of vertical MOSFET was revealed. The vicinity of DP near the drain end is found to reduce the charge sharing effects between source and drain that gives better gate control of the depletion region for short channel effect (SCE) suppression in nanodevice structure. 2009 Conference or Workshop Item PeerReviewed Saad, Ismail and Mohd. Ali Lee, Razak and A. Riyadi, Munawar and Ismail, Razali (2009) Design and simulation analysis of nanoscale vertical MOSFET technology. In: Proceeding of 2009 Student Conference on Research and Development (SCOReD 2009), 2009, UPM Serdang,. http://dx.doi.org/10.1109/SCORED.2009.5443109 |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Saad, Ismail Mohd. Ali Lee, Razak A. Riyadi, Munawar Ismail, Razali Design and simulation analysis of nanoscale vertical MOSFET technology |
| title | Design and simulation analysis of nanoscale vertical MOSFET technology |
| title_full | Design and simulation analysis of nanoscale vertical MOSFET technology |
| title_fullStr | Design and simulation analysis of nanoscale vertical MOSFET technology |
| title_full_unstemmed | Design and simulation analysis of nanoscale vertical MOSFET technology |
| title_short | Design and simulation analysis of nanoscale vertical MOSFET technology |
| title_sort | design and simulation analysis of nanoscale vertical mosfet technology |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| work_keys_str_mv | AT saadismail designandsimulationanalysisofnanoscaleverticalmosfettechnology AT mohdalileerazak designandsimulationanalysisofnanoscaleverticalmosfettechnology AT ariyadimunawar designandsimulationanalysisofnanoscaleverticalmosfettechnology AT ismailrazali designandsimulationanalysisofnanoscaleverticalmosfettechnology |