Verilog design of bist on AES256 processor core with FPGA implementation
Cryptography is very important to ensure secured data storage and transmission through encryption technique in this digital world. The most widely used cryptography algorithm is the Advanced Encryption Standard (AES) published in 2001. AES algorithm is fast and easy to be implemented, and it aims to...
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| Format: | Thesis |
| Language: | English |
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2008
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| Online Access: | http://eprints.utm.my/18136/1/HewKeanYungMFKE2008.pdf |
| _version_ | 1796855673935364096 |
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| author | Hew, Kean Yung |
| author_facet | Hew, Kean Yung |
| author_sort | Hew, Kean Yung |
| collection | ePrints |
| description | Cryptography is very important to ensure secured data storage and transmission through encryption technique in this digital world. The most widely used cryptography algorithm is the Advanced Encryption Standard (AES) published in 2001. AES algorithm is fast and easy to be implemented, and it aims to protect data and ensure privacy. Hence, AES hardware cannot afford any encryption failure which will corrupt the whole system. Built-In-Self-Test (BIST) introduced into the AES system will increase the system testability and reliability, which in turn will protect the system from attack and will incur less testing cost. This project aims to continue previous UTM student’s research on FPGA implementation of AES system in System-on-Chip (SoC) design. By extending further, a proposed AES hardware BIST design is incorporated into the AES processor core in Verilog RTL and FGPA implementation. This will be a valuable asset to UTM for future SoC researches on AES and BIST design. |
| first_indexed | 2024-03-05T18:32:02Z |
| format | Thesis |
| id | utm.eprints-18136 |
| institution | Universiti Teknologi Malaysia - ePrints |
| language | English |
| last_indexed | 2024-03-05T18:32:02Z |
| publishDate | 2008 |
| record_format | dspace |
| spelling | utm.eprints-181362018-07-23T05:45:49Z http://eprints.utm.my/18136/ Verilog design of bist on AES256 processor core with FPGA implementation Hew, Kean Yung TK Electrical engineering. Electronics Nuclear engineering Cryptography is very important to ensure secured data storage and transmission through encryption technique in this digital world. The most widely used cryptography algorithm is the Advanced Encryption Standard (AES) published in 2001. AES algorithm is fast and easy to be implemented, and it aims to protect data and ensure privacy. Hence, AES hardware cannot afford any encryption failure which will corrupt the whole system. Built-In-Self-Test (BIST) introduced into the AES system will increase the system testability and reliability, which in turn will protect the system from attack and will incur less testing cost. This project aims to continue previous UTM student’s research on FPGA implementation of AES system in System-on-Chip (SoC) design. By extending further, a proposed AES hardware BIST design is incorporated into the AES processor core in Verilog RTL and FGPA implementation. This will be a valuable asset to UTM for future SoC researches on AES and BIST design. 2008-10 Thesis NonPeerReviewed application/pdf en http://eprints.utm.my/18136/1/HewKeanYungMFKE2008.pdf Hew, Kean Yung (2008) Verilog design of bist on AES256 processor core with FPGA implementation. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering. |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Hew, Kean Yung Verilog design of bist on AES256 processor core with FPGA implementation |
| title | Verilog design of bist on AES256 processor core with FPGA implementation |
| title_full | Verilog design of bist on AES256 processor core with FPGA implementation |
| title_fullStr | Verilog design of bist on AES256 processor core with FPGA implementation |
| title_full_unstemmed | Verilog design of bist on AES256 processor core with FPGA implementation |
| title_short | Verilog design of bist on AES256 processor core with FPGA implementation |
| title_sort | verilog design of bist on aes256 processor core with fpga implementation |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| url | http://eprints.utm.my/18136/1/HewKeanYungMFKE2008.pdf |
| work_keys_str_mv | AT hewkeanyung verilogdesignofbistonaes256processorcorewithfpgaimplementation |