Verilog design of bist on AES256 processor core with FPGA implementation

Verilog design of bist on AES256 processor core with FPGA implementation

Cryptography is very important to ensure secured data storage and transmission through encryption technique in this digital world. The most widely used cryptography algorithm is the Advanced Encryption Standard (AES) published in 2001. AES algorithm is fast and easy to be implemented, and it aims to...

Full description

Bibliographic Details
Main Author:	Hew, Kean Yung
Format:	Thesis
Language:	English
Published:	2008
Subjects:	TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/18136/1/HewKeanYungMFKE2008.pdf

Similar Items

Verilog design of bist on AES256 processor core with FPGA implementation /
by: Hew, Kean Yung, 1981-, et al.
Published: (2008)

Verilog design of bist on AE256 processor core with FPGA implementation [electronic resources] /
by: Hew, Kean Yung, 1981-, et al.
Published: (2008)

Verilog design of a 256-bit AES crypto processor core
by: Lai, Yit Pin
Published: (2007)

An FPGA implementation of RSA processor core for public-key cryptosystem
by: Tan, Siang Lin
Published: (2001)

An AES tightly coupled hardware accelerator in an FPGA-based Embedded processor core
by: Hani, Mohamed Khalil, et al.
Published: (2009)

Register transfer level design of compression processor core using verilog hardware description language
by: Mohd. Sabri, Roslee
Published: (2007)

VHDL design of A 32-Bit RISC processor core for FPGA implementation
by: Marsono, Muhammad Nadzir
Published: (2001)

Verilog design of input/output processor with built-in-self-test
by: Goh, Keng Hoo
Published: (2007)

Design and implementation of 16 bit DSP core processor using field programmable gate array (FPGA)
by: Abdul Rahman, Abdul Aziz
Published: (2003)

Verilog design of A 256-BIT AES crypto processor core /
by: 246310 Lai, Yit Pin
Published: (2007)

Implementation of optimized low pass filter for ECG filtering using verilog
by: Samsudin, Nooraisyah N., et al.
Published: (2022)

A tightly coupled finite field arithmetic hardware in an FPGA-based embedded processor core for elliptic curve cryptography
by: Mohd. Hani, Mohamed Khalil, et al.
Published: (2009)

Design of a route lookup processor for implementation in a FPGA-based system-on chip (SoC)
by: Teh , J-Wing
Published: (2004)

Adaptive configurable transactional memory for multi-processor FPGA platforms
by: Sirkunan, J., et al.
Published: (2015)

FPGA-based design of a math co-processor for the Amir CPU
by: Tan, Arthur Foo Yen
Published: (2020)

Parallel scan in BIST environment
by: Yusuf, Rihana
Published: (2001)

Verilog modelling of Modbus TCP at 100 mbps
by: Tan, Zhe Jie
Published: (2022)

Implementation of direct torque control of induction machines utilizing Digital Signal Processor (DSP) and Field Programmable Gate Arrays (FPGA)
by: Toh, Chuen Ling
Published: (2005)

Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms
by: Sirkunan, J., et al.
Published: (2017)

Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation
by: Ismail, Mohd. Izuan
Published: (2006)

The Implementation of a pipelined floating-point cordic coprocessor on Nios Ii soft processor
by: Ibrahim, Muhammad Nasir, et al.
Published: (2015)

The implementation of a pipelined floating-point CORDIC coprocessor on NIOS II soft processor
by: Ibrahim, Muhammad Nasir, et al.
Published: (2015)

Multi-core 16-bit CPUs for PLC processor
by: Gan, Chi Qian
Published: (2022)

FPGA implementation for recurrent PSS
by: Othman, Siti Marhainis
Published: (2008)

Test register insertion at RTL based on reduced BIST
by: Paraman, N., et al.
Published: (2017)

Verilog design of A 256-BIT AES crypto processor core [electronic resource] /
by: 246310 Lai, Yit Pin
Published: (2007)

Rounded off unsigned constant division using add-shift in verilog
by: Fouziah Md Yassin, et al.
Published: (2016)

Modeling and simulation of graphene three branch junction using verilog-A
by: Chin, Ee Mei
Published: (2015)

Accelerated Verilog Simulator Using Application Specific Microprocessor
by: Tan Tze Sin, Tze Sin
Published: (2017)

FPGA implementation of metaheuristic optimization algorithm
by: Nurul Hazlina, Noordin, et al.
Published: (2023)

Implementation of harris corner detector on fpga
by: Al-Shatari, Mohammed Omar Awadh
Published: (2016)

Implementation of embedded in-circuit emulator for DLX processor
by: Bee Wooi, Khaw
Published: (2008)

Implementation of barrel shifter and multiplier for the DLX processor
by: Goh, Teng Sun
Published: (2008)

RTL design of SHA-512 processor core for secure message hashing
by: Chua, Lee Ping
Published: (2008)

Hardware implementation using FPGA for barcode reader
by: Marzuki, Ade Syaheda Wani
Published: (2008)

FPGA implementation of simulated kalman filter optimization algorithm
by: Nurul Hazlina, Noordin, et al.
Published: (2018)

FPGA Implementation of RSA Public-Key Cryptographic Coprocessor
by: Hani, Mohamed Khalil, et al.
Published: (2000)

Design and implementation of OFDM transmitter and receiver on FPGA hardware
by: Kadiran, Kamaru Adzha
Published: (2005)

New approach FPGA-based implementation of discontinuous SVPWM
by: Sutikno, Tole, et al.
Published: (2010)

FPGA implementation of naive bayes classifier for network security
by: Mohamad Zuki, Ahmad Zulzhafri
Published: (2018)