Asic design of a kohonen neural network microchip
This paper discusses the Kohonen neural network (KNN) processor and its KNN computation engine microchip. The ASIC design of the KNN processor adopts a novel implementation approach whereby the computation of the KNN algorithm is performed on the custom ASIC microchip and its operations are governed...
| Main Authors: | , |
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| Format: | Book Section |
| Language: | English |
| Published: |
IEEE
2004
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| Subjects: | |
| Online Access: | http://eprints.utm.my/2031/1/RajahKhalilHani2004__ASICDesignKohonenNeuralNetwork.pdf |
| Summary: | This paper discusses the Kohonen neural network (KNN) processor and its KNN computation engine microchip. The ASIC design of the KNN processor adopts a novel implementation approach whereby the computation of the KNN algorithm is performed on the custom ASIC microchip and its operations are governed by a FPGA based controller. Thus, the ASIC implementation of the KNN processor is derived through integration between a custom ASIC and FPGA. The 3.3V AMI 0.5um CO5M-D process technology was used to achieve the VLSI design of the computation engine microchip and the entire design adopted the BBX cell based methodology, which is a viable alternative to conventional ASIC methodology. |
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