Sub-micron technology development and system-on-chip (Soc) design - data compression core
Data compression removes redundancy from the source data and thereby increases storage capacity of a storage medium or efficiency of data transmission in a communication link. Although several data compression techniques have been implemented in hardware, they are not flexible enough to be embedded...
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| Format: | Monograph |
| Language: | English |
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Universiti Teknologi Malaysia
2002
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| Online Access: | http://eprints.utm.my/2919/1/72319.pdf |
| _version_ | 1825909310909054976 |
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| author | Husin, Nasir Sheikh |
| author_facet | Husin, Nasir Sheikh |
| author_sort | Husin, Nasir Sheikh |
| collection | ePrints |
| description | Data compression removes redundancy from the source data and thereby increases storage capacity of a storage medium or efficiency of data transmission in a communication link. Although several data compression techniques have been implemented in hardware, they are not flexible enough to be embedded in more complex applications. Data compression software meanwhile cannot support the demand of high-speed computing applications. Due to these deficiencies, in this project we develop a parameterized lossless universal data compression IP core for high-speed applications. The design of the core is based on the combination of Lempel-Ziv-Storer-Szymanski (LZSS) compression algorithm and Huffman coding. The resulting IP core offers a data-independent throughput that can process a symbol in every clock cycle. The design is described in parameterized VHDL code to enable a user to make a suitable compromise between resource constraints, operation speed and compression saving, so that it can be adapted for any target application. In implementation on Altera FLEX10KE FPGA device, the design offers a performance of 800 Mbps with an operating frequency of 50 MHz. This IP core is suitable for high-speed computing applications or for storage systems. |
| first_indexed | 2024-03-05T18:00:15Z |
| format | Monograph |
| id | utm.eprints-2919 |
| institution | Universiti Teknologi Malaysia - ePrints |
| language | English |
| last_indexed | 2024-03-05T18:00:15Z |
| publishDate | 2002 |
| publisher | Universiti Teknologi Malaysia |
| record_format | dspace |
| spelling | utm.eprints-29192017-09-10T04:22:25Z http://eprints.utm.my/2919/ Sub-micron technology development and system-on-chip (Soc) design - data compression core Husin, Nasir Sheikh TK Electrical engineering. Electronics Nuclear engineering Data compression removes redundancy from the source data and thereby increases storage capacity of a storage medium or efficiency of data transmission in a communication link. Although several data compression techniques have been implemented in hardware, they are not flexible enough to be embedded in more complex applications. Data compression software meanwhile cannot support the demand of high-speed computing applications. Due to these deficiencies, in this project we develop a parameterized lossless universal data compression IP core for high-speed applications. The design of the core is based on the combination of Lempel-Ziv-Storer-Szymanski (LZSS) compression algorithm and Huffman coding. The resulting IP core offers a data-independent throughput that can process a symbol in every clock cycle. The design is described in parameterized VHDL code to enable a user to make a suitable compromise between resource constraints, operation speed and compression saving, so that it can be adapted for any target application. In implementation on Altera FLEX10KE FPGA device, the design offers a performance of 800 Mbps with an operating frequency of 50 MHz. This IP core is suitable for high-speed computing applications or for storage systems. Universiti Teknologi Malaysia 2002 Monograph NonPeerReviewed application/pdf en http://eprints.utm.my/2919/1/72319.pdf Husin, Nasir Sheikh (2002) Sub-micron technology development and system-on-chip (Soc) design - data compression core. Technical Report. Universiti Teknologi Malaysia. (Unpublished) |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Husin, Nasir Sheikh Sub-micron technology development and system-on-chip (Soc) design - data compression core |
| title | Sub-micron technology development and system-on-chip (Soc) design - data compression core |
| title_full | Sub-micron technology development and system-on-chip (Soc) design - data compression core |
| title_fullStr | Sub-micron technology development and system-on-chip (Soc) design - data compression core |
| title_full_unstemmed | Sub-micron technology development and system-on-chip (Soc) design - data compression core |
| title_short | Sub-micron technology development and system-on-chip (Soc) design - data compression core |
| title_sort | sub micron technology development and system on chip soc design data compression core |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| url | http://eprints.utm.my/2919/1/72319.pdf |
| work_keys_str_mv | AT husinnasirsheikh submicrontechnologydevelopmentandsystemonchipsocdesigndatacompressioncore |