RTL design of modular arithmetic processor (MAP) core for prime finite field arithmetic, GF(P)

RTL design of modular arithmetic processor (MAP) core for prime finite field arithmetic, GF(P)

Bibliographic Details
Main Author:	Liew, Meng Wei
Format:	Thesis
Published:	2008
Subjects:	TK Electrical engineering. Electronics Nuclear engineering

Similar Items

RTL design of modular arithmetic processor (MAP) core for prime finite field arithmetic, GF(P) /
by: 195724 Liew, Meng Wei
Published: (2008)

RTL design of modular arithmetic processor (MAP) core for prime finite field arithmetic, GF(P) [electronic resource] /
by: 195724 Liew, Meng Wei
Published: (2008)

A tightly coupled finite field arithmetic hardware in an FPGA-based embedded processor core for elliptic curve cryptography
by: Mohd. Hani, Mohamed Khalil, et al.
Published: (2009)

RTL design of SHA-512 processor core for secure message hashing
by: Chua, Lee Ping
Published: (2008)

Arithmetic logic unit design for silicon nanowire field-effect transistors logic
by: Mohd. Munir Zahari, Nor Hafizah
Published: (2015)

Load flow analysis uncertainty treatment via fuzzy arithmetic
by: Ayub, Zatul Akmar
Published: (2009)

Cortical networks of executive function during mental arithmetic task
by: Hashim, S., et al.
Published: (2015)

A reconfigurable arithmetic processor
by: Fiske, James Alexander Stuart
Published: (2005)

Brain functional connectivity and power spectrum analyses during mental arithmetic
by: Hashim, Syazreen, et al.
Published: (2015)

CNFET-based design ternary logic design and arithmetic circuit simulation using HSPICE
by: Ee, Poey Guan
Published: (2015)

Test register insertion at RTL based on reduced BIST
by: Paraman, N., et al.
Published: (2017)

Cognitive function assessment in young adult based on mental arithmetic trail making and stroop tasks
by: Hashim, Syazreen
Published: (2016)

Thermometer code based modular arithmetic
by: Vun, Chan Hua, et al.
Published: (2013)

RTL implementation of one-sided jacobi algorithm for singular value decomposition
by: Wan Mohamad, Wan Ahmad Zainie
Published: (2016)

Automated-tuned hyper-parameter deep neural network by using arithmetic optimization algorithm for Lorenz chaotic system
by: Nurnajmin Qasrina Ann, ., et al.
Published: (2023)

Design of an advanced encryption standard crypto-processor core for field programmable gate array implementation
by: Ismail, Mohd. Izuan
Published: (2006)

Correct-by-construction finite field arithmetic in Coq
by: Philipoom, Jade (Jade D.)
Published: (2018)

Multi-core 16-bit CPUs for PLC processor
by: Gan, Chi Qian
Published: (2022)

Parallel operated hybrid Arithmetic-Salp swarm optimizer for optimal allocation of multiple distributed generation units in distribution networks
by: Memon, Zeeshan Anjum, et al.
Published: (2022)

Design and implementation of 16 bit DSP core processor using field programmable gate array (FPGA)
by: Abdul Rahman, Abdul Aziz
Published: (2003)

An FPGA implementation of RSA processor core for public-key cryptosystem
by: Tan, Siang Lin
Published: (2001)

Verilog design of bist on AES256 processor core with FPGA implementation
by: Hew, Kean Yung
Published: (2008)

VHDL design of A 32-Bit RISC processor core for FPGA implementation
by: Marsono, Muhammad Nadzir
Published: (2001)

Block-based neural network mapping on graphics processor unit
by: Ong, Chin Tong
Published: (2015)

Arithmetic of finite fields /
by: 313927 Small, Charles
Published: (1991)

VHDL modelling and asic design of a shortest-path processor core for network routing
by: Teoh, Giap Seng
Published: (2003)

Rtl Implementation Of Secure Hash Algorithm 3 (Sha-3) Towards Smaller Area
by: Lim , Yen Ruen
Published: (2017)

Register transfer level design of compression processor core using verilog hardware description language
by: Mohd. Sabri, Roslee
Published: (2007)

A VLSI computing structure array processor
by: Loh, Sun Meng
Published: (1993)

Error coding for arithmetic processors /
by: 461125 Rao, Thammavarapu R. N.
Published: (1974)

Arithmetic coding for finite-state noiseless channels
Published: (2003)

ARM processor emulator
by: Mohd. Hashim, Mohamad Hasruzairin
Published: (2015)

Asic implementation of low latency montgomery modular exponentiation
by: Liew, Pui Yen
Published: (2022)

Hardware-based biometric encryption implementation with Gauss-Jordan algorithm accelerator core in field programmable gate arrays
by: Liew, Tek Yee
Published: (2011)

USB soft core with altera Nios processor
by: Cheah, Chee Teong
Published: (2007)

Workshop arithmetic
by: Castle, Frank, 1856-1928
Published: (1962)

Finite impulse response filter design on distributed arithmetic architecture
by: Abu Zaharin, Muhamad Iqbal
Published: (2012)

A tightly coupled finite field arithmetic hardware in an FPGA-based embedded processor core for elliptic curve cryptography /
by: Mohamed Khalil Hani, author, et al.
Published: (2008)

High performance ladder rung processor
by: Aspar, Zulfakar
Published: (2008)

Estimation of core loss in transformer by using finite element method
by: Muhammad Qusyairi, Abdul Nasib
Published: (2012)