Software and hardware co-simulation platform for image processing
Nowadays, modern SoCs have larger scale and complexity. Modelling hardware design archicteture of SoCs normally required RTL design. Since, the system design is getting larger, it is usually partitioned into two parts: software and hardware. For the sack of achieving real time performance, it is ess...
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| Format: | Thesis |
| Language: | English |
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2014
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| Online Access: | http://eprints.utm.my/48616/1/JohnnyKongJakKanMFKE2014.pdf |
| _version_ | 1796859355870527488 |
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| author | Kong, Johnny Jak Kan |
| author_facet | Kong, Johnny Jak Kan |
| author_sort | Kong, Johnny Jak Kan |
| collection | ePrints |
| description | Nowadays, modern SoCs have larger scale and complexity. Modelling hardware design archicteture of SoCs normally required RTL design. Since, the system design is getting larger, it is usually partitioned into two parts: software and hardware. For the sack of achieving real time performance, it is essential to map some of the algorithms into hardware. Previously, the hardware and software design of a system are done by different people. Therefore, the design lifecycle is longer. Now, market pressures on short design cycle, maintainability and reusability of system design. To reduce design cycle, a new method must be applied. SystemVerilog is the extension of Verilog HDL that improved with a lot of new features added. Direct programming interface (DPI) is one of the new features whereas it allow SV call C function and vice versa. This work proposed to use Altera-Modelsim simulator to run co-simulation on several test cases: 16- bit unsigned adder, greater common divisor (GCD), 9-tap FIR filter and binary median filter. All the hardware design modelling are using SystemVerilog due to DPI technique can only work with SV. 16-bit unsigned adder and GCD test cases are the startup work before a more complex and real world case studies are applied. 9-tap FIR filter is designed and the input data are passed from random number generator from C function. The output of FIR fitler are verified with C function. Due to window size of median filter is small, line buffer technique is applied in this work. It is a straight forward method and suit for design processing window in digital hardware. The proposed work has overcome the problems faced when running co-simulation based on Modelsim simulator using DPI technique. |
| first_indexed | 2024-03-05T19:25:57Z |
| format | Thesis |
| id | utm.eprints-48616 |
| institution | Universiti Teknologi Malaysia - ePrints |
| language | English |
| last_indexed | 2024-03-05T19:25:57Z |
| publishDate | 2014 |
| record_format | dspace |
| spelling | utm.eprints-486162020-03-02T07:19:36Z http://eprints.utm.my/48616/ Software and hardware co-simulation platform for image processing Kong, Johnny Jak Kan TA Engineering (General). Civil engineering (General) Nowadays, modern SoCs have larger scale and complexity. Modelling hardware design archicteture of SoCs normally required RTL design. Since, the system design is getting larger, it is usually partitioned into two parts: software and hardware. For the sack of achieving real time performance, it is essential to map some of the algorithms into hardware. Previously, the hardware and software design of a system are done by different people. Therefore, the design lifecycle is longer. Now, market pressures on short design cycle, maintainability and reusability of system design. To reduce design cycle, a new method must be applied. SystemVerilog is the extension of Verilog HDL that improved with a lot of new features added. Direct programming interface (DPI) is one of the new features whereas it allow SV call C function and vice versa. This work proposed to use Altera-Modelsim simulator to run co-simulation on several test cases: 16- bit unsigned adder, greater common divisor (GCD), 9-tap FIR filter and binary median filter. All the hardware design modelling are using SystemVerilog due to DPI technique can only work with SV. 16-bit unsigned adder and GCD test cases are the startup work before a more complex and real world case studies are applied. 9-tap FIR filter is designed and the input data are passed from random number generator from C function. The output of FIR fitler are verified with C function. Due to window size of median filter is small, line buffer technique is applied in this work. It is a straight forward method and suit for design processing window in digital hardware. The proposed work has overcome the problems faced when running co-simulation based on Modelsim simulator using DPI technique. 2014 Thesis NonPeerReviewed application/pdf en http://eprints.utm.my/48616/1/JohnnyKongJakKanMFKE2014.pdf Kong, Johnny Jak Kan (2014) Software and hardware co-simulation platform for image processing. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering. http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:81447?queryType=vitalDismax&query=Software+and+hardware+co-simulation+platform+for+image+processing&public=true |
| spellingShingle | TA Engineering (General). Civil engineering (General) Kong, Johnny Jak Kan Software and hardware co-simulation platform for image processing |
| title | Software and hardware co-simulation platform for image processing |
| title_full | Software and hardware co-simulation platform for image processing |
| title_fullStr | Software and hardware co-simulation platform for image processing |
| title_full_unstemmed | Software and hardware co-simulation platform for image processing |
| title_short | Software and hardware co-simulation platform for image processing |
| title_sort | software and hardware co simulation platform for image processing |
| topic | TA Engineering (General). Civil engineering (General) |
| url | http://eprints.utm.my/48616/1/JohnnyKongJakKanMFKE2014.pdf |
| work_keys_str_mv | AT kongjohnnyjakkan softwareandhardwarecosimulationplatformforimageprocessing |