Network partitioning and GA heuristic crossover for NOC application mapping

Network-on-chip (NoC) has been introduced as a promising on-chip communication architecture to support many IP (intellectual property) cores on a single chip. Application mapping of IP cores onto a NoC topology is considered as a NP-hard problem. The increasing number of IP cores makes NoC applicati...

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Main Authors: Tei, Y. Z., Marsono, M. N., Shaikh-Husin, N., Hau, Y. W.
Format: Conference or Workshop Item
Published: 2013
Subjects:
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author Tei, Y. Z.
Marsono, M. N.
Shaikh-Husin, N.
Hau, Y. W.
author_facet Tei, Y. Z.
Marsono, M. N.
Shaikh-Husin, N.
Hau, Y. W.
author_sort Tei, Y. Z.
collection ePrints
description Network-on-chip (NoC) has been introduced as a promising on-chip communication architecture to support many IP (intellectual property) cores on a single chip. Application mapping of IP cores onto a NoC topology is considered as a NP-hard problem. The increasing number of IP cores makes NoC application mapping more challenging to obtain optimum core-to-topology mapping. This paper proposes a genetic algorithm approach that incorporates network partitioning and heuristic crossover techniques to improve the NoC application mapping. Our experiment on VOPD (video object plane decoder) shows that our proposed method results in only 0.2% to 0.8% communication cost difference compared to global optimal mapping and 6% better communication cost compared to technique using conventional GA.
first_indexed 2024-03-05T19:29:28Z
format Conference or Workshop Item
id utm.eprints-51193
institution Universiti Teknologi Malaysia - ePrints
last_indexed 2024-03-05T19:29:28Z
publishDate 2013
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spelling utm.eprints-511932017-08-15T06:14:48Z http://eprints.utm.my/51193/ Network partitioning and GA heuristic crossover for NOC application mapping Tei, Y. Z. Marsono, M. N. Shaikh-Husin, N. Hau, Y. W. TK Electrical engineering. Electronics Nuclear engineering Network-on-chip (NoC) has been introduced as a promising on-chip communication architecture to support many IP (intellectual property) cores on a single chip. Application mapping of IP cores onto a NoC topology is considered as a NP-hard problem. The increasing number of IP cores makes NoC application mapping more challenging to obtain optimum core-to-topology mapping. This paper proposes a genetic algorithm approach that incorporates network partitioning and heuristic crossover techniques to improve the NoC application mapping. Our experiment on VOPD (video object plane decoder) shows that our proposed method results in only 0.2% to 0.8% communication cost difference compared to global optimal mapping and 6% better communication cost compared to technique using conventional GA. 2013 Conference or Workshop Item PeerReviewed Tei, Y. Z. and Marsono, M. N. and Shaikh-Husin, N. and Hau, Y. W. (2013) Network partitioning and GA heuristic crossover for NOC application mapping. In: Proceedings - IEEE International Symposium on Circuits and Systems. http://dx.doi.org/10.1109/ISCAS.2013.6572074
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Tei, Y. Z.
Marsono, M. N.
Shaikh-Husin, N.
Hau, Y. W.
Network partitioning and GA heuristic crossover for NOC application mapping
title Network partitioning and GA heuristic crossover for NOC application mapping
title_full Network partitioning and GA heuristic crossover for NOC application mapping
title_fullStr Network partitioning and GA heuristic crossover for NOC application mapping
title_full_unstemmed Network partitioning and GA heuristic crossover for NOC application mapping
title_short Network partitioning and GA heuristic crossover for NOC application mapping
title_sort network partitioning and ga heuristic crossover for noc application mapping
topic TK Electrical engineering. Electronics Nuclear engineering
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AT marsonomn networkpartitioningandgaheuristiccrossoverfornocapplicationmapping
AT shaikhhusinn networkpartitioningandgaheuristiccrossoverfornocapplicationmapping
AT hauyw networkpartitioningandgaheuristiccrossoverfornocapplicationmapping