A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree
This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized for the placement and area optimization of macro-cell layout in very large scaled integrated (VLSI) design. Three...
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| Format: | Conference or Workshop Item |
| Published: |
Faculty of Electrical Engineering
2008
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| Subjects: |
| _version_ | 1796854612625457152 |
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| author | Rahim At Samsuddin, H. A. Ab. Rahman, A. A. H. Andaljayalakshmi, G. Ahmad, R. B. |
| author_facet | Rahim At Samsuddin, H. A. Ab. Rahman, A. A. H. Andaljayalakshmi, G. Ahmad, R. B. |
| author_sort | Rahim At Samsuddin, H. A. |
| collection | ePrints |
| description | This paper proposes an optimization approach for
macro-cell placement which minimizes the chip area
size. A binary tree method for non-slicing tree
construction process is utilized for the placement and
area optimization of macro-cell layout in very large
scaled integrated (VLSI) design. Three different types
of genetic algorithms: simple genetic algorithm (SGA),
steady-state algorithm (SSGA) and adaptive genetic
algorithm (AGA) are employed in order to examine
their performances in converging to their global
minimums. Experimental results on Microelectronics
Center of North Carolina (MCNC) benchmark
problems show that the developed algorithm achieves
an acceptable performance quality to the slicing
floorplan. Furthermore, the robustness of genetic
algorithm also has been investigated in order to
validate the performance stability in achieving the
optimal solution for every runtime. This algorithm
demonstrates that SSGA converges to the optimal
result faster than SGA and AGA. Besides that, SSGA
also outperforms SGA and AGA in terms of robustness |
| first_indexed | 2024-03-05T18:16:40Z |
| format | Conference or Workshop Item |
| id | utm.eprints-9961 |
| institution | Universiti Teknologi Malaysia - ePrints |
| last_indexed | 2024-03-05T18:16:40Z |
| publishDate | 2008 |
| publisher | Faculty of Electrical Engineering |
| record_format | dspace |
| spelling | utm.eprints-99612020-02-29T13:40:39Z http://eprints.utm.my/9961/ A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree Rahim At Samsuddin, H. A. Ab. Rahman, A. A. H. Andaljayalakshmi, G. Ahmad, R. B. TK Electrical engineering. Electronics Nuclear engineering This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized for the placement and area optimization of macro-cell layout in very large scaled integrated (VLSI) design. Three different types of genetic algorithms: simple genetic algorithm (SGA), steady-state algorithm (SSGA) and adaptive genetic algorithm (AGA) are employed in order to examine their performances in converging to their global minimums. Experimental results on Microelectronics Center of North Carolina (MCNC) benchmark problems show that the developed algorithm achieves an acceptable performance quality to the slicing floorplan. Furthermore, the robustness of genetic algorithm also has been investigated in order to validate the performance stability in achieving the optimal solution for every runtime. This algorithm demonstrates that SSGA converges to the optimal result faster than SGA and AGA. Besides that, SSGA also outperforms SGA and AGA in terms of robustness Faculty of Electrical Engineering 2008 Conference or Workshop Item PeerReviewed Rahim At Samsuddin, H. A. and Ab. Rahman, A. A. H. and Andaljayalakshmi, G. and Ahmad, R. B. (2008) A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree. In: Proceedings of the International Conference on Computer and Communication Engineering 2008, May 13-15, 2008, Kuala Lumpur, Malaysia. http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:127756 |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Rahim At Samsuddin, H. A. Ab. Rahman, A. A. H. Andaljayalakshmi, G. Ahmad, R. B. A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree |
| title | A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree |
| title_full | A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree |
| title_fullStr | A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree |
| title_full_unstemmed | A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree |
| title_short | A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree |
| title_sort | genetic algorithm approach to vlsi macro cell non slicing floorplans using binary tree |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
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