A bit-serial architecture for a multiplierless DCT
This paper describes the implementation of a multiplierless 1-D DCT which is also applicable to a 2-D computation. The key idea is based on the binary DCT of which multipliers are replaced by lifting parameters that essentially are shifts and adds. For low power applications and smaller hardware siz...
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Universiti Utara Malaysia
2003
|
| Subjects: | |
| Online Access: | https://repo.uum.edu.my/id/eprint/1019/1/S._Choomchuay.pdf |
| _version_ | 1825739742731304960 |
|---|---|
| author | Choomchuay, S. Timakul, S. |
| author_facet | Choomchuay, S. Timakul, S. |
| author_sort | Choomchuay, S. |
| collection | UUM |
| description | This paper describes the implementation of a multiplierless 1-D DCT which is also applicable to a 2-D computation. The key idea is based on the binary DCT of which multipliers are replaced by lifting parameters that essentially are shifts and adds. For low power applications and smaller hardware size, a bit-serial architecture was invoked in the implementation of such an algorithm. Varying data word length, MSE obtained form our approach and some similar algorithms are also investigated and reported. |
| first_indexed | 2024-07-04T05:14:39Z |
| format | Article |
| id | uum-1019 |
| institution | Universiti Utara Malaysia |
| language | English |
| last_indexed | 2024-07-04T05:14:39Z |
| publishDate | 2003 |
| publisher | Universiti Utara Malaysia |
| record_format | eprints |
| spelling | uum-10192010-09-05T07:27:14Z https://repo.uum.edu.my/id/eprint/1019/ A bit-serial architecture for a multiplierless DCT Choomchuay, S. Timakul, S. QA75 Electronic computers. Computer science This paper describes the implementation of a multiplierless 1-D DCT which is also applicable to a 2-D computation. The key idea is based on the binary DCT of which multipliers are replaced by lifting parameters that essentially are shifts and adds. For low power applications and smaller hardware size, a bit-serial architecture was invoked in the implementation of such an algorithm. Varying data word length, MSE obtained form our approach and some similar algorithms are also investigated and reported. Universiti Utara Malaysia 2003 Article PeerReviewed application/pdf en https://repo.uum.edu.my/id/eprint/1019/1/S._Choomchuay.pdf Choomchuay, S. and Timakul, S. (2003) A bit-serial architecture for a multiplierless DCT. Journal of ICT, 2 (1). pp. 15-30. ISSN 1675-414X http://jict.uum.edu.my |
| spellingShingle | QA75 Electronic computers. Computer science Choomchuay, S. Timakul, S. A bit-serial architecture for a multiplierless DCT |
| title | A bit-serial architecture for a multiplierless DCT |
| title_full | A bit-serial architecture for a multiplierless DCT |
| title_fullStr | A bit-serial architecture for a multiplierless DCT |
| title_full_unstemmed | A bit-serial architecture for a multiplierless DCT |
| title_short | A bit-serial architecture for a multiplierless DCT |
| title_sort | bit serial architecture for a multiplierless dct |
| topic | QA75 Electronic computers. Computer science |
| url | https://repo.uum.edu.my/id/eprint/1019/1/S._Choomchuay.pdf |
| work_keys_str_mv | AT choomchuays abitserialarchitectureforamultiplierlessdct AT timakuls abitserialarchitectureforamultiplierlessdct AT choomchuays bitserialarchitectureforamultiplierlessdct AT timakuls bitserialarchitectureforamultiplierlessdct |