Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review by Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski, Kazimierz Krzywicki

“…Methods for reducing power consumption in circuits of finite state machines (FSMs) are discussed in this review. …”
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Using Codes of Output Collections for Hardware Reduction in Circuits of LUT-Based Finite State Machines by Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki, Kamil Mielcarek

“…A method is proposed which aims to reduce the hardware in FPGA-based circuits of Mealy finite state machines (FSMs). The proposed method is a type of structural decomposition method. …”
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Structural Decomposition in FSM Design: Roots, Evolution, Current State—A Review by Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki

Subjects: “…finite state machine…”
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Encoding of Terms in EMB-Based Mealy FSMs by Alexander Barkalov, Larysa Titarenko, Małgorzata Mazurkiewicz, Kazimierz Krzywicki

Subjects: “…mealy finite state machine…”
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Reducing LUT Count for FPGA-Based Mealy FSMs by Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki

“…Very often, digital systems include sequential blocks which can be represented using a model of Mealy finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and power consumption. …”
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Improving LUT count of FPGA-based sequential blocks by Alexander Barkalov, Larysa Titarenko, Małgorzata Mazurkiewicz, Kazimierz Krzywicki

“…Very often, a digital system includes sequential blocks which can be represented using a model of the finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and consumed energy. …”
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Improving Characteristics of LUT-Based Mealy FSMs with Twofold State Assignment by Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki, Svetlana Saburova

“…This article is devoted to a case when sequential blocks are represented by models of Mealy finite state machines (FSMs). The performance (maximum operating frequency) is one of the most important characteristics of an FSM circuit. …”
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Improving the Characteristics of Multi-Level LUT-Based Mealy FSMs by Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki, Svetlana Saburova

“…In the article, we discuss a case when Mealy finite state machines (FSMs) describe the behavior of sequential blocks. …”
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Improving Hardware in LUT-Based Mealy FSMs by Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki

“…The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs (COs) for representing both FSM state variables and outputs. …”
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Improving the Spatial Characteristics of Three-Level LUT-Based Mealy FSM Circuits by Alexander Barkalov, Larysa Titarenko, Małgorzata Mazurkiewicz, Kazimierz Krzywicki

“…The devices are represented by models of Mealy finite state machines (FSMs). Thesee are so-called MPY FSMs based on two methods of structural decomposition (the replacement of inputs and encoding of output collections). …”
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Using a Double-Core Structure to Reduce the LUT Count in FPGA-Based Mealy FSMs by Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki

“…A method is proposed which aims at reducing the numbers of look-up table (LUT) elements in logic circuits of Mealy finite state machines (FSMs). The FSMs with twofold state assignment are discussed. …”
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Improving Characteristics of LUT-Based Three-Block Mealy FSMs’ Circuits by Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki, Svetlana Saburova

“…In this paper, we discuss the implementation of Mealy finite state machines (FSMs) by circuits consisting of look-up tables (LUT). …”
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Improving Characteristics of LUT-Based Sequential Blocks for Cyber-Physical Systems by Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki

“…In this article, we discuss a case when Mealy finite state machines (FSMs) represent behaviour of sequential devices. …”
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Reducing Hardware in LUT-Based Mealy FSMs with Encoded Collections of Outputs by Alexander Barkalov, Larysa Titarenko, Małgorzata Mazurkiewicz

“…A method is proposed that is focused on reducing the chip area occupied by logic elements creating the circuit of Mealy finite state machines (FSMs). The proposed method is aimed at FSM circuits implemented with internal resources of field-programmable gate arrays (FPGA). …”
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Improving Characteristics of FPGA-Based FSMs Representing Sequential Blocks of Cyber-Physical Systems by Alexander Barkalov, Larysa Titarenko, Kazimierz Krzywicki, Svetlana Saburova

“…This work proposes a method for hardware reduction in circuits of Mealy finite state machines (FSMs). The circuits are implemented as networks of interconnected look-up table (LUT) elements. …”
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Hardware Reduction for FSMs With Extended State Codes by Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Malgorzata Mazurkiewicz

“…A method is proposed for reducing chip area occupied by logic circuits of FPGA-based Mealy finite state machines (FSMs). The proposed method aims at optimization of FSM circuits implemented with look-up table (LUT) elements of FPGA chip. …”
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Optimization of a Moore Automaton Circuit in a Mixed Element Basis by Alexander Barkalov, Larysa Titarenko, Oleksandr Golovin, Oleksandr Matvienko

“…To represent the law of functioning of a control unit, the models of the Moore and Mealy finite state machines (FSM) are used. When synthesizing circuits of FSMs, it is necessary to solve a number of optimization problems, such as the reducing hardware amount, increasing performance, minimizing power consumption, joint optimization of hardware-temporal characteristics. …”
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