Design Method of Vertical Lattice Loop Structure for Parasitic Inductance Reduction in a GaN HEMTs-Based Converter by Si-Seok Yang, Sung-Soo Min, Chan-Hyeok Eom, Rae-Young Kim, Gi-Young Lee

“…In contrast, the driving voltage and threshold voltage are relatively low compared to conventional power semiconductor devices, so a reliable circuit design is required. …”
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Lumped Parameter Modeling Based Power Loop Analysis Technique of Power Circuit Board with Wide Conduction Area for WBG Semiconductors by Gi-Young Lee, Min-Shin Cho, Rae-Young Kim

“…However, due to the high rate-of-rise of voltage (<i>dv/dt</i>) and of current (<i>di/dt</i>), compared to conventional Si-based power semiconductor devices, the reliability of the device is greatly affected by the parasitic inductance component in the switching loop. …”
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