In Situ Study on Cu-to-Cu Thermal Compression Bonding by Tongjun Niu, Ke Xu, Chao Shen, Tianyi Sun, Justin Oberst, Carol A. Handwerker, Ganesh Subbarayan, Haiyan Wang, Xinghang Zhang

“…Cu-to-Cu thermal compression bonding (TCB) has emerged as a promising solution for ultrafine pitch packaging in 3D integrated circuit technologies. Despite the progress made by conventional Cu-to-Cu TCB methods in achieving good mechanical strength of the Cu bonds, the bonding processes generally require high temperature and high pressure, which may degrade the performance and reliability of the device. …”
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CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor by Wenhui Wang, Ke Li, Jun Lan, Mei Shen, Zhongrui Wang, Xuewei Feng, Hongyu Yu, Kai Chen, Jiamin Li, Feichi Zhou, Longyang Lin, Panpan Zhang, Yida Li

“…Abstract The development of high-performance oxide-based transistors is critical to enable very large-scale integration (VLSI) of monolithic 3-D integrated circuit (IC) in complementary metal oxide semiconductor (CMOS) backend-of-line (BEOL). …”
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Superior High Transistor’s Effective Mobility of 325 cm²/V-s by 5 nm Quasi-Two-Dimensional SnON nFET by Pheiroijam Pooja, Chun Che Chien, Albert Chin

“…SnON nFETs with record-breaking µ_eff and quasi-2D thickness enable a potential monolithic three-dimensional (3D) integrated circuit (IC) and embedded memory for 3D biological brain-mimicking structures.…”
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The Effects of Etchant on via Hole Taper Angle and Selectivity in Selective Laser Etching by Jonghyeok Kim, Byungjoo Kim, Jiyeon Choi, Sanghoon Ahn

“…Glass has unique properties that make it suitable for 3D integrated circuit (IC) interposers, which include low permittivity, high transparency, and adjustable thermal expansion coefficient. …”
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Exceedingly High Performance Top-Gate P-Type SnO Thin Film Transistor with a Nanometer Scale Channel Layer by Te Jui Yen, Albert Chin, Vladimir Gritsenko

“…Implementing high-performance n- and p-type thin-film transistors (TFTs) for monolithic three-dimensional (3D) integrated circuit (IC) and low-DC-power display is crucial. …”
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Effect of copper TSV annealing on via protrusion for TSV wafer fabrication by Heryanto, A., Putra, W. N., Trigg, Alastair David, Gao, S., Kwon, W. S., Che, Faxing, Ang, X. F., Wei, J., Made, Riko I., Gan, Chee Lip, Pey, Kin Leong

“…Three-dimensional (3D) integrated circuit (IC) technologies are receiving increasing attention due to their capability to enhance microchip function and performance. …”
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Synergistically Enhanced Performance and Reliability of Abrupt Metal‐Oxide Heterojunction Transistor by Pengfei Wang, Huan Yang, Jiye Li, Xiaohui Zhang, Lei Wang, Juncheng Xiao, Bin Zhao, Shengdong Zhang, Lei Lu

“…Abstract The large‐area low‐temperature processing capability and versatile characteristics of amorphous oxide semiconductor (AOS) thin‐film transistors (TFTs) are highly expected to promote the developments of next‐generation displays, 3D integrated circuit (3DIC), flexible chips, and electronics. …”
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Monolithic 3D integration of back-end compatible 2D material FET on Si FinFET by Shi-Xian Guan, Tilo H. Yang, Chih-Hao Yang, Chuan-Jie Hong, Bor-Wei Liang, Kristan Bryan Simbulan, Jyun-Hong Chen, Chun-Jung Su, Kai-Shin Li, Yuan-Liang Zhong, Lain-Jong Li, Yann-Wen Lan

“…This work clearly proves the integration compatibility of 2D materials with Si-based devices, encouraging the further development of monolithic 3D integrated circuits.…”
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Design automation and analysis of three-dimensional integrated circuits by Das, Shamik, 1977-

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Through-silicon-via (TSV) design, fabrication and characterization for 3D IC applications by Zhang, Lin

“…In addition, TSV can also be designed and embedded in a 3D integrated circuit (IC) stack to assist in heat removal, which is a critical challenge facing 3D IC. …”
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Integrated through-silicon-via-based inductor design in buck converter for improved efficiency by A. Namoune, R. Taleb, N. Mansour, M. R. Benzidane, A. Boukortt

“…Through-silicon-via (TSV) is one of the most important components of 3D integrated circuits. Similar to two-dimensional circuits, the performance evaluation of 3D circuits depends on both the quality factor and inductance. …”
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Ant Colony Algorithm for Energy Saving to Optimize Three-Dimensional Bonding Chips’ Thermal Layout by Bihao Sun, Peizhi Yang, Zhiyuan Zhu

“…The simulation results show that the optimization of the thermal layout of 3D integrated circuits can be well realized by adjusting the algorithm parameters. …”
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TSV‐based common‐mode noise‐suppressing filter design and implementation by Zhensong Li, Huan Liu, Yunheng Sun, Yang Yang, Min Miao, Shenglin Ma, Yufeng Jin

“…Abstract A through‐silicon via (TSV)‐based, common‐mode, noise‐suppressing filter (TSV‐CMF) with the silicon interposer process is proposed to improve the electromagnetic compatibility in 3D integrated circuits. A differential fifth‐order T‐model low‐pass filter prototype circuit for transmission lines with common inductance is used to characterize and design the stopband and the corresponding two transmission zeros for the common mode (CM). …”
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An end-to-end convolutional neural network for automated failure localisation and characterisation of 3D interconnects by Priya Paulachan, Jörg Siegert, Ingo Wiesler, Roland Brunner

“…Abstract The advancement in the field of 3D integration circuit technology leads to new challenges for quality assessment of interconnects such as through silicon vias (TSVs) in terms of automated and time-efficient analysis. …”
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Electrical and Mechanical Analysis of Different TSV Geometries by Il Ho Jeong, Alireza Eslami Majd, Jae Pil Jung, Nduka Nnamdi Ekere

“…Through-silicon via (TSV) is an important component for implementing 3-D packages and 3-D integrated circuits as the TSV technology allows stacked silicon chips to interconnect through direct contact to help facilitate high-speed signal processing. …”
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Research and implementation of AC resistance calculation method for TSV array by Zhao Jinglong, Miao Min

“…Through Silicon Via(TSV), as a key interconnection technology in 3D integrated circuits, is used to connect input and output of chips in different layers. …”
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A Review of Recent Developments in “On-Chip” Embedded Cooling Technologies for Heterogeneous Integrated Applications by Srikanth Rangarajan, Scott N. Schiffres, Bahgat Sammakia

“…Heterogeneous integration (HI) can be at the chip level (a single chip with multiple hotspots), in multi-chip modules, or in vertically stacked three-dimensional (3D) integrated circuits. Flux values have increased exponentially with a simultaneous reduction in chip size and a significant increase in performance, leading to increased heat dissipation. …”
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Femtosecond-precision electronic clock distribution in CMOS chips by injecting frequency comb-extracted photocurrent pulses by Minji Hyun, Hayun Chung, Woongdae Na, Jungwon Kim

“…This work shows the potential of optical frequency combs for distributing high-quality clock signals inside high-performance integrated circuits, including 3D integrated circuits.…”
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Thermal stability and bonding interface in Cu/SiO2 hybrid bonding on nano-twinned copper by Jou-Chun Ou, Yi-Yun Tsai, Ting-Chun Lin, Chin-Li Kao, Shih-Chieh Hsiao, Fei-Ya Huang, Jui-Chao Kuo

“…Cu/SiO2 hybrid bonding has been developed for the application of heterogeneous bond interfaces in 3D integrated circuits in which thermal stability and bonding behavior are important. …”
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Temperature-Aware Floorplanning for Fixed-Outline 3D ICs by Tianming Ni, Hao Chang, Shidong Zhu, Lin Lu, Xueyun Li, Qi Xu, Huaguo Liang, Zhengfeng Huang

“…Thermal characteristics have been considered as one of the most challenging problems in 3D integrated circuits (3D ICs). The vertically stacked multiple layers of active devices cause a rapid increase of power density and the thermal conductivity of the dielectric layers inserted between device layers for insulation is quite low compared to silicon and metal, which make the peak temperature of 3D ICs rise, leading to the performance degradation. …”
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