Research on CMOS latchup in quarter micron technology by Leong, Kam Chew.

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Cell-based array for deep sub-micron technologies by Oey, James Boe-Kian, 1980-

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Interconnect modeling and optimization in deep sub-micron technologies by Sotiriadis, Paul Peter P. (Paul Peter Peter-Paul), 1973-

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Study of VIA-related failures in sub-micron technologies by Chia, Gary Yue Choy.

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SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview by Waqas Gul, Maitham Shams, Dhamin Al-Khalili

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Electrostatic Discharge Protection Circuit Design In Deep Sub-Micron Technology For Automotive Application by Ng, Yit Ming

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Sub-micron technology development and system-on-chip (Soc) design - data compression core by Husin, Nasir Sheikh

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Study of robust package strength characterization of memory packages for handheld application by Vance Liu, Chien-Ming Chen, Joyce Chen, Min-Hua Chung, Chong Leong Gan

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Design evaluation of microelectronics devices using focused ion beam technology by Yeo, Swee Hock.

“…Miniaturisation of IC chips has forced many IC manufacturers to go to and beyond deep-sub-micron technology. The present IC technology still stands at less than 0.35 micron. …”
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Threshold Switching by Bipolar Avalanche Multiplication in Ovonic Chalcogenide Glasses by Paolo Fantini, Nicola Polino, Andrea Ghetti, Daniele Ielmini

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Three-dimensional (3D) finite element modeling of stress distribution and migration in Cu interconnects by Anson Heryanto

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Qualitative Analysis of MOS Circuits by Williams, Brian C.

“…With the push towards sub-micron technology, transistor models have become increasingly complex. …”
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Initial study on optical tomographic instrumentation system based on CMOS area image sensors by Idroas, Mariani, Mohd. Najib, Suhaila, Ibrahim, M. Nasir, Abdul Rahim, Ruzairi, Badri Mansor, Muhammad Saiful

“…This paper explains the initial study on activating the CMOS area image sensor model MT9D1C12STC manufactured by Micron Technology.…”

Technological sustainable materials and enabling in semiconductor memory industry: A review by Chong Leong Gan, Min-Hua Chung, Yung-Sheng Zou, Chen-Yu Huang, Hem Takiar

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Gate leakage logic detection for analog CMOS circuit by Kamisian, Izam, Ibrahim, Muhamad Faisal, A'ain, Abu Khari, Lee, Yuen Tat, Tan, Terrence Huat Hin

“…In micron technology node, Igate is not a big issue to circuit designer due to its negligible value. …”
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Characterization of optical interconnects by Sam, Shiou Lin, 1976-

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Content-filtering AI systems–limitations, challenges and regulatory approaches by Marsoof, Althaf, Luco, Andrés, Tan, Harry, Joty, Shafiq

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Analysis of High-Temperature Data Retention in 3D Floating-Gate nand Flash Memory Arrays by Gerardo Malavena, Mattia Giulianini, Luca Chiavarone, Alessandro S. Spinelli, Christian Monzio Compagnoni

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A Comparative Study of n- and p-Channel FeFETs with Ferroelectric HZO Gate Dielectric by Paul Jacob, Pooja C. Patil, Shan Deng, Kai Ni, Khushwant Sehra, Mridula Gupta, Manoj Saxena, David MacMahon, Santosh Kurinec

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Design and analysis of an efficient low power low delay low leakage clock keeper domino logic by Kurumaiah N, M. Kezia Joseph, P. Chandra Sekhar

“…The design and development of CMOS VLSI semiconductor circuits employing deep sub-micron technology has faced significant challenges, primarily in terms of propagation delay and power consumption. …”
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