Design of the 16 - bit pipeline risc processor in FPGA / by 226231 Loo, Ai Choo, Mohamed Khalil Mohd. Hani, supervisor, Fakulti Kejuruteraan Elektrik

Subjects: “…Pipelining (Electronics)…”

Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations by Kumar Sambhav Pandey, Hitesh Shrimali

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An Effective Detection Approach for Phishing URL Using ResMLP by S. Remya, Manu J. Pillai, Kajal K. Nair, Somula Rama Subbareddy, Yong Yun Cho

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A Network Traffic Classification Method for Class-Imbalanced Data by Xiaohui Guan, Yaguan Qian

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A Network Traffic Classification Method for Class-Imbalanced Data by Xiaohui Guan, Yaguan Qian

Subjects: “…attack traffic;class imbalance;classifiers pipelining ensemble…”
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Convolutional Neural Networks using FPGA-based Pipelining by Gheni A. Ali, ahmed hussein ali

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A Hybrid Neural Based Dynamic Branch Prediction Unit by Gheni A. Ali

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Delay Time Analysis of Reconfigurable Firewall Unit by Tomoaki Sato, Phichet Moungnoul, Masa-Aki Fukase

Subjects: “…Wave-Pipelining…”
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A Novel Throughput Enhancement Method for Deep Learning Applications on Mobile Devices With Heterogeneous Processors by Choonghoon Park, Soonhoi Ha

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Partitioning and Scheduling DSP Applications with Maximal Memory Access Hiding by Sha Edwin Hsing-Mean, Wang Yuke, Wang Zhong

Subjects: “…loop pipelining…”
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Combination of Reduction Detection Using TOPSIS for Gene Expression Data Analysis by Jogeswar Tripathy, Rasmita Dash, Binod Kumar Pattanayak, Sambit Kumar Mishra, Tapas Kumar Mishra, Deepak Puthal

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Exploração de paralelismo à nível de instruções e de tarefas em uma arquitetura de processamento não convencional by Aparecida Medeiros, Ana Luisa Medeiros, Márcio Eduardo Kreutz

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A Novel High-Speed Configurable Viterbi Decoder for Broadband Access by Benaissa Mohammed, Zhu Yiqun

Subjects: “…pipelining…”
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SPADOCK: Adaptive Pipeline Technology for Web System using WebSocket by Aries RICHI, Riri Fitri SARI

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Deep Learning Compiler Load Balancing Optimization Method for Model Training by WANG Li, GAO Kai, ZHAO Yaqian, LI Rengang, CAO Fang, GUO Zhenhua

Subjects: “…model training; compiler optimization; load balancing; hierarchical scheduling; automatic pipelining…”
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FPGA BASED ASYNCHRONOUS PIPELINED MB-OFDM UWB TRANSMITTER BACKEND MODULES by M. Santhi, G. Lakshminarayanan

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BioLegato: a programmable, object-oriented graphic user interface by Graham Alvare, Abiel Roche-Lima, Brian Fristensky

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Simplifying Physical Realization of Gaussian Particle Filters with Block-Level Pipeline Control by Bolić Miodrag, Hong Sangjin, Djurić Petar M

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Network Transfer of Control Data: An Application of the NIST SMART DATA FLOW by Vincent Stanford, Martial Michel, Olivier Galibert

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A reconfigurable and compact subpipelined architecture for AES encryption and decryption by Ke Li, Hua Li, Graeme Mund

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