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  1. 221

    Development of single board computer based on 32-bit 5-stage pipeline RISC processor by Koay, Boon Wooi

    Published 2009
    “…ISA (Instruction Set Architecture) of RISC(Reduced Instructions Set Computer) processor is enhanced to cover control instruction. …”
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    Thesis
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    Siwi cooperates with Par-1 kinase to resolve the autoinhibitory effect of Papi for Siwi-piRISC biogenesis by Hiromi Yamada, Kazumichi M. Nishida, Yuka W. Iwasaki, Yosuke Isota, Lumi Negishi, Mikiko C. Siomi

    Published 2022-03-01
    “…Siwi-piRISC protects the germline genome from DNA damage caused by selfish movement of transposons by suppressing their expression. …”
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    Article
  14. 234

    Factorii de risc ce pot determina recurența insuficienței tricuspide după o corecţie reconstructivă by Vitalie Moscalu, Gheorghe Manolache, Vladislav Morozan, Vitalie Moscalu, Iurie Guzgan, Aureliu Batrînac

    Published 2019-03-01
    “…Prin metode statistice au fost stabiliți factorii de risc ce pot influenţa recurenţa IT după annuloplastie. …”
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    Article
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    Exploratory graph analysis on the Connor–Davidson Resilience Scale (CD-RISC) among older adults in China by Yujie Wang, Jixiang Xu, Shitong Yang, Junjia Jiang, Junling Gao

    Published 2023-11-01
    “…This study aims to examine the dimensional structure underlying the Connor–Davidson Resilience Scale (CD-RISC) among Chinese older adults. Exploratory Graph Analysis (EGA) was used to evaluate the dimensional structure of CD-RISC in two large samples: training sample (n = 11,493) and cross-validation sample (n = 7662). …”
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    Article
  17. 237

    DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training by Angelo Garofalo, Yvan Tortorella, Matteo Perotti, Luca Valente, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti

    Published 2022-01-01
    “…We present DARKSIDE, a System-on-Chip with a heterogeneous cluster of eight RISC-V cores enhanced with 2-b to 32-b mixed-precision integer arithmetic. …”
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    Article
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